[PATCH 2/5] t210: do not enable PLLE and UPHY PLL HW PWRSEQ

Stephen Warren swarren at wwwdotorg.org
Tue Mar 17 18:29:32 CET 2020

On 3/16/20 1:40 PM, twarren at nvidia.com wrote:
> From: JC Kuo <jckuo at nvidia.com>
> This commit removes the programming sequence that enables PLLE and UPHY
> PLL hardware power sequencers. Per TRM, boot software should enable PLLE
> and UPHY PLLs in software controlled power-on state and should power
> down PLL before jumping into kernel or the next stage boot software.
> Adds call to board_cleanup_before_linux to facilitate this.

This directly contradicts what's in Tegra_X1_TRM_DP07225001_v1.3p.pdf,
pages 1340/1341, which is what the code currently implements. Was a
newer internal-only TRM published that changed the recommended
programming flow?

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