[PATCH 2/9] ram: stm32mp1: display result for software read DQS gating

[Patrice CHOTARD]

On 3/6/20 11:14 AM, Patrick Delaunay wrote:
> Display result information for software read DQS gating, the tuning 0
> which be used by CubeMX DDR tuning tools.
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---
>
>  drivers/ram/stm32mp1/stm32mp1_tuning.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c
> index 4e1c1fab54..e3e6f0f79c 100644
> --- a/drivers/ram/stm32mp1/stm32mp1_tuning.c
> +++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c
> @@ -1182,15 +1182,17 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
>  				 dqs_gate_values[byte][0],
>  				 dqs_gate_values[byte][1]);
>  			pr_debug("*******the nominal values were system latency: 0  phase: 2*******\n");
> -			set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
> -			set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
>  		}
>  	} else {
>  		/* if intermitant, restore defaut values */
>  		pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
> -		set_r0dgsl_delay(phy, byte, 0);
> -		set_r0dgps_delay(phy, byte, 2);
> +		dqs_gate_values[byte][0] = 0;
> +		dqs_gate_values[byte][1] = 2;
>  	}
> +	set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
> +	set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
> +	printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n",
> +	       byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]);
>  
>  	/* return 0 if intermittent or if both left_bound
>  	 * and right_bound are not found

Acked-by: Patrice Chotard <patrice.chotard at st.com>

Thanks

Patrice