Antwort: Re: Re: x86: apl: PCI enumeration issue

[Bernhard Messerklinger]

Hi Bin,

>Hi Bernhard,
>
>On Mon, Mar 30, 2020 at 4:25 PM Bernhard Messerklinger
><bernhard.messerklinger at br-automation.com> wrote:
>>
>> Hi Bin,
>>
>> >Hi Bernhard,
>> >
>> >On Mon, Mar 30, 2020 at 3:35 PM Bernhard Messerklinger
>> ><bernhard.messerklinger at br-automation.com> wrote:
>> >>
>> >> Hi Simon, Bin,
>> >>
>> >> I am facing problems with the PCI enumeration at SPL loader
>stage.
>> >> On our HW we have PCIe x2 port connected to a FPGA. Since SPL
>does
>> >pci
>> >> enumeration before FSP-S has been called the enumeration of the
>> >second port of
>> >> the pci x2 connection causes the system to hang.
>> >
>> >Do you know why the 2nd port hang happens, but not the 1st port?
>Is
>> >that because in order to get 2nd port working something is done in
>> >FSP-S?
>>
>> I know that the problem happens because of the PCIe FIT tool
>configuration.
>> If I change the configuration to PCIe x1 on all root ports of the
>SoC the
>> issue doesn't occur.
>> I think FSP-S hides the second port because it's no real PCIe root
>port,
>
>That's not common. If FSP-S is hiding the 2nd port, it should not be
>visible in the PCI configuration space. Do you know if this is a bug
>of the silicon or it just behaves like this?

No I think the point is, that at the time (SPL) where the first
pci enumeration is done the FSP-S init is not done.
The FSP-S init is called later in the main u-boot.
After FSP-S init it works fine.

>>> it's just the second lane of the first port. I also did some
>research in the
>> intel FSP-S code. In the FSP-S code some not documented fuse
>registers are
>> accessed and then the second port is deactivated depending of the
>FIT
>> configuration.
>
>Regards,
>Bin
>

Regards, 
Bernhard