[PATCH 6/6] rockchip: rk3328: Add support for ROC-RK3328-CC board

Jagan Teki jagan at amarulasolutions.com
Mon Mar 30 19:44:13 CEST 2020


Hi Chen-Yu,

On Fri, Mar 27, 2020 at 10:12 AM Chen-Yu Tsai <wens at kernel.org> wrote:
>
> From: Chen-Yu Tsai <wens at csie.org>
>
> The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
> card size development board based on the Rockchip RK3328 SoC, with:
>
>   - 1/2/4 GB DDR4 DRAM
>   - eMMC connector for optional module
>   - micro SD card slot
>   - 1 x USB 3.0 host port
>   - 2 x USB 2.0 host port
>   - 1 x USB 2.0 OTG port
>   - HDMI video output
>   - TRRS connector with audio and composite video output
>   - gigabit Ethernet
>   - consumer IR receiver
>   - debug UART pins
>
> The ROC-RK3328-CC has the enable pin of the SD card power switch tied
> to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
> muxed by default. SDMMC0_PWREN is an active high signal controlled by
> the MMC controller, however the switch enable is active low, and
> pulled low (enabled) by default to make things work on boot.
>
> As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
> power to the card. The default GPIO state for the pin is pull-down and
> input, which doesn't require extra configuration when paired with the
> external pull-down and active low switch.
>
> Thus we make a custom target for this board and do the muxing in its
> spl_board_init() function.
>
> The device tree file is synced from the Linux kernel next-20200324.
>
> Signed-off-by: Chen-Yu Tsai <wens at csie.org>
> ---

[snip]

> diff --git a/board/firefly/roc-cc-rk3328/MAINTAINERS b/board/firefly/roc-cc-rk3328/MAINTAINERS
> new file mode 100644
> index 000000000000..f2318e71ac33
> --- /dev/null
> +++ b/board/firefly/roc-cc-rk3328/MAINTAINERS
> @@ -0,0 +1,7 @@
> +ROC-RK3328-CC
> +M:      Loic Devulder <ldevulder at suse.com>
> +M:     Chen-Yu Tsai <wens at csie.org>
> +S:      Maintained
> +F:     board/firefly/roc-cc-rk3328/
> +F:      configs/roc-rk3328-cc_defconfig
> +F:      arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
> diff --git a/board/firefly/roc-cc-rk3328/Makefile b/board/firefly/roc-cc-rk3328/Makefile
> new file mode 100644
> index 000000000000..1550b5f5f16e
> --- /dev/null
> +++ b/board/firefly/roc-cc-rk3328/Makefile
> @@ -0,0 +1 @@
> +obj-y  := board.o
> diff --git a/board/firefly/roc-cc-rk3328/board.c b/board/firefly/roc-cc-rk3328/board.c
> new file mode 100644
> index 000000000000..eca58c86b53e
> --- /dev/null
> +++ b/board/firefly/roc-cc-rk3328/board.c
> @@ -0,0 +1,38 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2020 Chen-Yu Tsai <wens at csie.org>
> + */
> +#include <asm/io.h>
> +
> +#include <asm/arch-rockchip/grf_rk3328.h>
> +#include <asm/arch-rockchip/hardware.h>
> +
> +#if defined(CONFIG_SPL_BUILD)
> +
> +#define GRF_BASE       0xFF100000
> +
> +enum {
> +       GPIO_0_D6_GPIO  = 0   << 12,
> +       GPIO_0_D6_MASK  = 0x3 << 12
> +};
> +
> +/*
> + * The ROC-RK3328-CC has the enable pin of the SD card power switch tied
> + * to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
> + * muxed by default. SDMMC0_PWREN is an active high signal controlled by
> + * the MMC controller, however the switch enable is active low, and
> + * pulled low (enabled) by default to make things work on boot.
> + *
> + * As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
> + * power to the card. The default GPIO state for the pin is pull-down and
> + * input, which doesn't require extra configuration when paired with the
> + * external pull-down and active low switch.
> + */
> +void spl_board_init(void)
> +{
> +       struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
> +
> +       rk_clrsetreg(&grf->gpio0d_iomux, GPIO_0_D6_MASK, GPIO_0_D6_GPIO);
> +}

So, this seem toggle the bit 12, 13 of GRF_GPIO0D_IOMUX so-that it
operate like a gpio(not like default sdmmc0_pwrenm1), isn't it
required for the next stages like U-Boot proper and Linux? these has
vcc_sd node where it operates a fixed regulator to active low the same
pin.

gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;

Jagan.


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