Antwort: [PATCH v3 11/29] x86: apl: Add Global NVS table header

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg at chromium.org> schrieb: -----

>An: u-boot at lists.denx.de
>Von: "Simon Glass" <sjg at chromium.org>
>Datum: 31.03.2020 01:14
>Kopie: "Andy Shevchenko" <andriy.shevchenko at linux.intel.com>,
>"Wolfgang Wallner" <wolfgang.wallner at br-automation.com>, "Leif
>Lindholm" <leif at nuviainc.com>, "Simon Glass" <sjg at chromium.org>, "Bin
>Meng" <bmeng.cn at gmail.com>
>Betreff: [PATCH v3 11/29] x86: apl: Add Global NVS table header
>
>Add the C version of this header. It includes a few Chrome OS bits
>which
>are disabled for a normal build.
>
>Signed-off-by: Simon Glass <sjg at chromium.org>
>---
>
>Changes in v3:
>- Fix stray #endif
>
>Changes in v2:
>- Drop the Chrome OS pieces
>- Rename the 'coreboot' console to 'U-Boot'
>
> .../include/asm/arch-apollolake/global_nvs.h  | 36
>+++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 arch/x86/include/asm/arch-apollolake/global_nvs.h
>
>diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h
>b/arch/x86/include/asm/arch-apollolake/global_nvs.h
>new file mode 100644
>index 00000000000..5bde837a755
>--- /dev/null
>+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h
>@@ -0,0 +1,36 @@
>+/* SPDX-License-Identifier: GPL-2.0+ */
>+/*
>+ * Copyright (C) 2015-2017 Intel Corp.
>+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
>+ * Copyright Google LLC 2019
>+ *
>+ * Modified from coreboot apollolake/include/soc/nvs.h
>+ */
>+
>+#ifndef _GLOBAL_NVS_H_
>+#define _GLOBAL_NVS_H_
>+
>+struct __packed acpi_global_nvs {
>+	/* Miscellaneous */
>+	u8	pcnt; /* 0x00 - Processor Count */
>+	u8	ppcm; /* 0x01 - Max PPC State */
>+	u8	lids; /* 0x02 - LID State */
>+	u8	pwrs; /* 0x03 - AC Power State */
>+	u8	dpte; /* 0x04 - Enable DPTF */
>+	u32	cbmc; /* 0x05 - 0x08 - U-Boot Console */
>+	u64	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
>+	u64	gpei; /* 0x11 - 0x18 - GPE Wake Source */
>+	u64	nhla; /* 0x19 - 0x20 - NHLT Address */
>+	u32	nhll; /* 0x21 - 0x24 - NHLT Length */
>+	u32	prt0; /* 0x25 - 0x28 - PERST_0 Address */
>+	u8	scdp; /* 0x29 - SD_CD GPIO portid */
>+	u8	scdo; /* 0x2A - GPIO pad offset relative to the community */
>+	u8	uior; /* 0x2B - UART debug controller init on S3 resume */
>+	u8	ecps; /* 0x2C - SGX Enabled status */
>+	u64	emna; /* 0x2D - 0x34 EPC base address */
>+	u64	elng; /* 0x35 - 0x3C EPC Length */
>+	u8	unused[195];
>+	u8		unused2[0xf00];

Nit 1: Something is still wrong with the indentation of unused2.

Nit 2: Could you please add comments on why the values 195 and 0xf00 were
       chosen? I would assume 195 was selected so that unused2 starts on
       a 256-byte boundary? But that is only a guess.

>+};
>+
>+#endif /* _GLOBAL_NVS_H_ */
>-- 
>2.26.0.rc2.310.g2932bb562d-goog
>

Reviewed-by: Wolfgang Wallner <wolgang.wallner at br-automation.com>