[PATCH v7 01/22] misc: add driver for the SiFive otp controller

Pragnesh Patel pragnesh.patel at sifive.com
Sat May 2 17:42:35 CEST 2020

Hi Jagan,

>-----Original Message-----
>From: Jagan Teki <jagan at amarulasolutions.com>
>Sent: 02 May 2020 21:07
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot-Denx <u-boot at lists.denx.de>; Atish Patra
><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Bin
>Meng <bmeng.cn at gmail.com>; Paul Walmsley <paul.walmsley at sifive.com>;
>Troy Benjegerdes <troy.benjegerdes at sifive.com>; Anup Patel
><anup.patel at wdc.com>; Sagar Kadam <sagar.kadam at sifive.com>; Rick Chen
><rick at andestech.com>; Tero Kristo <t-kristo at ti.com>; Simon Glass
><sjg at chromium.org>; Adam Ford <aford173 at gmail.com>; Eugen Hristev
><eugen.hristev at microchip.com>; Peng Fan <peng.fan at nxp.com>; Finley Xiao
><finley.xiao at rock-chips.com>; Kever Yang <kever.yang at rock-chips.com>
>Subject: Re: [PATCH v7 01/22] misc: add driver for the SiFive otp controller
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>On Sat, May 2, 2020 at 3:37 PM Pragnesh Patel <pragnesh.patel at sifive.com>
>> Added a misc driver to handle OTP memory in SiFive SoCs.
>> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
>> ---
>>  drivers/misc/Kconfig      |   7 +
>>  drivers/misc/Makefile     |   1 +
>>  drivers/misc/sifive-otp.c | 273
>> ++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 281 insertions(+)
>>  create mode 100644 drivers/misc/sifive-otp.c
>> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
>> 766402745d..03464f1010 100644
>> --- a/drivers/misc/Kconfig
>> +++ b/drivers/misc/Kconfig
>> @@ -68,6 +68,13 @@ config ROCKCHIP_OTP
>>           addressing and a length or through child-nodes that are generated
>>           based on the e-fuse map retrieved from the DTS.
>> +config SIFIVE_OTP
>> +       bool "SiFive eMemory OTP driver"
>> +       depends on RISCV && MISC
>This can be something like this.
>config SIFIVE_OTP
>       bool "SiFive eMemory OTP driver"
>       depends on SIFIVE_FU540

This config option is not FU540 specific but it's for all SiFive SoCs.

>       select MISC

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