[PATCH 6/8] ARM: imx8m: Fix reset in SPL on NXP iMX8MP EVK

[Harald Seiler]

On Mon, 2020-05-04 at 12:18 -0300, Fabio Estevam wrote:
> On Mon, May 4, 2020 at 12:05 PM Harald Seiler <hws at denx.de> wrote:
> 
> > "Failed to find clock node. Check device tree" comes from spl_board_init()
> > in board/freescale/imx8mp_evk/spl.c; line 56:
> > 
> >         ret = uclass_get_device_by_name(UCLASS_CLK,
> >                                         "clock-controller at 30380000",
> >                                         &dev);
> > 
> > I see that wdog1 references the same clock here:
> > 
> > arch/arm/dts/imx8mp.dtsi; line 222:
> > 
> >         wdog1: watchdog at 30280000 {
> >                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
> >                 reg = <0x30280000 0x10000>;
> >                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> >                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
> >                 status = "disabled";
> >         };
> > 
> > So the two issues are very likely related.  The relevant clock's node is
> > also enabled for SPL so I think the driver might be missing here.  Maybe
> > you need to add
> > 
> >     CONFIG_SPL_CLK_IMX8MP=y
> > 
> > to your defconfig?
> 
> I tried like this:
> 
> --- a/configs/imx8mp_evk_defconfig
> +++ b/configs/imx8mp_evk_defconfig
> @@ -57,7 +57,9 @@ CONFIG_ENV_IS_IN_MMC=y
>  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>  CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
>  CONFIG_SPL_DM=y
> +CONFIG_SPL_CLK_COMPOSITE_CCF=y
>  CONFIG_CLK_COMPOSITE_CCF=y
> +CONFIG_SPL_CLK_IMX8MP=y
>  CONFIG_CLK_IMX8MP=y
>  CONFIG_MXC_GPIO=y
>  CONFIG_DM_PCA953X=y
> 
> but still only prints:
> 
> U-Boot SPL 2020.07-rc1-00014-g8142a97d54-dirty (May 04 2020 - 12:16:25 -0300)

With or without the revert?

-- 
Harald