[PATCH v4 05/12] phy: atheros: Clarify the intention of ar8021_config

[Tom Rini]

On Thu, May 07, 2020 at 12:11:52AM +0200, Michael Walle wrote:

> From: Vladimir Oltean <vladimir.oltean at nxp.com>
> 
> Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
> the other bit positions, just like the other PHYs in the family do.
> Therefore, it is not necessary to hardcode the reserved values, but
> instead simply follow the read-modify-write procedure from the common
> function.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>
> Acked-by: Joe Hershberger <joe.hershberger at ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
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