rk3399 single channel lpddr4 setup

[Jagan Teki]

Hi Jack,

On Fri, Apr 24, 2020 at 1:08 AM Jack Mitchell <ml at embed.me.uk> wrote:
>
> On 23/04/2020 12:38, Jagan Teki wrote:
> > On Tue, Apr 21, 2020 at 7:54 PM Jack Mitchell <ml at embed.me.uk> wrote:
> >>
> >> Has anyone worked with an rk3399 based board with a single channel RAM
> >> setup? I've looked at the current code and made some changes for only
> >> setting up a single channel which basically consists of altering the
> >> loops down to one channel, however u-boot is hanging while checking for
> >> a successful frequency change here:
> >>
> >>>        /* change freq */
> >>>        writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
> >>>               (fn << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
> >>>        while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
> >>>                ;
> >>>
> >>
> >> I believe this is due to waiting for both channels to switch frequency
> >> which will never happen as there is only a single channel setup.
> >>
> >> Has anyone worked with a similar setup, or have any further
> >> documentation as the TRM only has a fairly basic register listing.
> >
> > I have tried single-channel with DDR3 which is present on NOE4, I
> > believe the existing code does handle single channel for LPDDR4, can
> > you enable debugs and check on existing code. Usually the code cannot
> > go and try channel 1.
> >
> > Jagan.
> >
>
> Hi Jagen,
>
> So I've managed to confirm it working in single channel with DDR4 on a
> Khadas Edge-V by shorting the reset line to RAM chip on the second
> channel, u-boot successfully comes up while only detecting a single chip.
>
> We've compared our board design with the NEO4 and the biggest notable
> difference we can see is that they power the second channel even though
> it's unused, while in our design we don't, leaving it completely
> disconnected. I believe this is what's causing our difficulties. Are you
> aware of any workaround which instructs the SoC to completely ignore the
> second channel?

I did try to check this any dram register to route SoC to inform about
channeling, but unfortunately I couldn't find any relevenet. Maybe
Kever, YouMin might help.

Jagan.