[PATCH v7 19/22] sifive: dts: fu540: Enable L2 Cache in U-Boot

[Pragnesh Patel]

>-----Original Message-----
>From: Jagan Teki <jagan at amarulasolutions.com>
>Sent: 10 May 2020 15:02
>To: Pragnesh Patel <pragnesh.patel at sifive.com>
>Cc: U-Boot-Denx <u-boot at lists.denx.de>; Atish Patra
><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Bin
>Meng <bmeng.cn at gmail.com>; Paul Walmsley <paul.walmsley at sifive.com>;
>Troy Benjegerdes <troy.benjegerdes at sifive.com>; Anup Patel
><anup.patel at wdc.com>; Sagar Kadam <sagar.kadam at sifive.com>; Rick Chen
><rick at andestech.com>
>Subject: Re: [PATCH v7 19/22] sifive: dts: fu540: Enable L2 Cache in U-Boot
>
>[External Email] Do not click links or attachments unless you recognize the
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>
>On Sun, May 3, 2020 at 12:57 PM Pragnesh Patel
><pragnesh.patel at sifive.com> wrote:
>>
>> Hi jagan,
>>
>> >-----Original Message-----
>> >From: Jagan Teki <jagan at amarulasolutions.com>
>> >Sent: 02 May 2020 22:43
>> >To: Pragnesh Patel <pragnesh.patel at sifive.com>
>> >Cc: U-Boot-Denx <u-boot at lists.denx.de>; Atish Patra
>> ><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>;
>Bin
>> >Meng <bmeng.cn at gmail.com>; Paul Walmsley
><paul.walmsley at sifive.com>;
>> >Troy Benjegerdes <troy.benjegerdes at sifive.com>; Anup Patel
>> ><anup.patel at wdc.com>; Sagar Kadam <sagar.kadam at sifive.com>; Rick
>Chen
>> ><rick at andestech.com>
>> >Subject: Re: [PATCH v7 19/22] sifive: dts: fu540: Enable L2 Cache in
>> >U-Boot
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >On Sat, May 2, 2020 at 10:12 PM Pragnesh Patel
>> ><pragnesh.patel at sifive.com>
>> >wrote:
>> >>
>> >> Hi Jagan,
>> >>
>> >> >-----Original Message-----
>> >> >From: Jagan Teki <jagan at amarulasolutions.com>
>> >> >Sent: 02 May 2020 21:49
>> >> >To: Pragnesh Patel <pragnesh.patel at sifive.com>
>> >> >Cc: U-Boot-Denx <u-boot at lists.denx.de>; Atish Patra
>> >> ><atish.patra at wdc.com>; Palmer Dabbelt
><palmerdabbelt at google.com>;
>> >Bin
>> >> >Meng <bmeng.cn at gmail.com>; Paul Walmsley
>> ><paul.walmsley at sifive.com>;
>> >> >Troy Benjegerdes <troy.benjegerdes at sifive.com>; Anup Patel
>> >> ><anup.patel at wdc.com>; Sagar Kadam <sagar.kadam at sifive.com>; Rick
>> >Chen
>> >> ><rick at andestech.com>
>> >> >Subject: Re: [PATCH v7 19/22] sifive: dts: fu540: Enable L2 Cache
>> >> >in U-Boot
>> >> >
>> >> >[External Email] Do not click links or attachments unless you
>> >> >recognize the sender and know the content is safe
>> >> >
>> >> >On Sat, May 2, 2020 at 3:39 PM Pragnesh Patel
>> >> ><pragnesh.patel at sifive.com>
>> >> >wrote:
>> >> >>
>> >> >> Add L2 cache node to enable cache ways from U-Boot
>> >> >
>> >> >This and 20/22 doesn't relate to SPL MMC boot?, if yes please send
>> >> >them separately.
>> >>
>> >> This series is for replacing FSBL and all the patches are related to that.
>> >> IMHO it's better to add all FSBL functionality in one series.
>> >
>> >You mean does it break existing FSBL flow? if yes add proper commit
>> >message, but I am able to boot SPL MMC w/o this?
>>
>> Cache ways are enabled by FSBL also and if I will send cache ways
>> patches separately then it will a duplicate way of enabling cache ways if
>someone using FSBL.
>
>Sorry I didn't get you.
>
>If we cannot include these changes does U-Boot SPL break existing FSBL?

No, U-Boot SPL does not break without this.

As of now, we also want to support FSBL flow and FSBL also enabled the Cache ways for U-Boot
proper and if someone use this patches of L2 cache enable ways will FSBL then it will be a duplicate
work of cache enable ways.

>
>Jagan.