[Uboot-stm32] [PATCH 9/9] ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL

[Patrice CHOTARD]

Hi Patrick

On 4/21/20 5:11 PM, Patrick Delaunay wrote:
> This patch allows to switch the CPU frequency to 800MHz on the
> ST Microelectronics board (DK1/DK2 and EV1) when it supported by the HW
> (for STM32MP15xD and STM32MP15xF).
>
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---
>
>  arch/arm/dts/stm32mp15-u-boot.dtsi       | 10 ++++++++++
>  arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi |  9 ---------
>  arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi |  9 ---------
>  3 files changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi
> index e0b1223de8..497c1a01ec 100644
> --- a/arch/arm/dts/stm32mp15-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi
> @@ -63,6 +63,16 @@
>  	u-boot,dm-pre-reloc;
>  };
>  
> +&cpu0_opp_table {
> +	u-boot,dm-spl;
> +	opp-650000000 {
> +		u-boot,dm-spl;
> +	};
> +	opp-800000000 {
> +		u-boot,dm-spl;
> +	};
> +};
> +
>  &gpioa {
>  	u-boot,dm-pre-reloc;
>  };
> diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> index 5844d41c53..97d5ea43c3 100644
> --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
> @@ -122,15 +122,6 @@
>  		CLK_LPTIM45_LSE
>  	>;
>  
> -	/* VCO = 1300.0 MHz => P = 650 (CPU) */
> -	pll1: st,pll at 0 {
> -		compatible = "st,stm32mp1-pll";
> -		reg = <0>;
> -		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
> -		frac = < 0x800 >;
> -		u-boot,dm-pre-reloc;
> -	};
> -
>  	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
>  	pll2: st,pll at 1 {
>  		compatible = "st,stm32mp1-pll";
> diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> index ed2f024be9..9f9aa4ac65 100644
> --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
> @@ -119,15 +119,6 @@
>  		CLK_LPTIM45_LSE
>  	>;
>  
> -	/* VCO = 1300.0 MHz => P = 650 (CPU) */
> -	pll1: st,pll at 0 {
> -		compatible = "st,stm32mp1-pll";
> -		reg = <0>;
> -		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
> -		frac = < 0x800 >;
> -		u-boot,dm-pre-reloc;
> -	};
> -
>  	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
>  	pll2: st,pll at 1 {
>  		compatible = "st,stm32mp1-pll";

Reviewed-by: Patrice Chotard <patrice.chotard at st.com>

Thanks

Patrice