[PATCH v4 2/2] arm: stm32mp: activate data cache on DDR in SPL

[Patrick DELAUNAY]

Hi

> From: Patrick DELAUNAY <patrick.delaunay at st.com>
> Sent: jeudi 30 avril 2020 16:30
> 
> Activate cache on DDR to improve the accesses to DDR used by SPL:
> - CONFIG_SPL_BSS_START_ADDR
> - CONFIG_SYS_SPL_MALLOC_START
> 
> Cache is configured only when DDR is fully initialized, to avoid speculative access
> and issue in get_ram_size().
> Data cache is deactivated at the end of SPL, to flush the data cache and the TLB.
> 
> Reviewed-by: Patrice Chotard <patrice.chotard at st.com>
> Signed-off-by: Patrick Delaunay <patrick.delaunay at st.com>
> ---
> 
> Changes in v4:
> - fix commit message and add Patrice Chotard reviewed-by
> 
> Changes in v3:
> - remove debug message "bye"
> 
> Changes in v2:
> - new
> 
>  arch/arm/mach-stm32mp/spl.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 

Applied to u-boot-stm/master, thanks!

Regards

Patrick