[PATCH v5 05/16] arm64: dts: rk3399: Move u2phy into root port

[Kever Yang]

Hi Jagan, Frank,

On 2020/5/13 下午3:15, Frank Wang wrote:
> From: Jagan Teki <jagan at amarulasolutions.com>
>
> Yes, This is changing the actual device tree u2phy
> structure but the problem with the current Generic
> PHY subsystem is unable to find PHY if the PHY node
> is not part of the root structure.

I don't understand for this, it should be able to bind the device when

dm scan fdt.

Rockchip code always can use this node directly without modify, could

you check again?


Thanks,

- Kever

>
> This will be reverted,
> - Once we support the PHY subsystem to get the PHY
>    even though it is not part of the root node or
> - any other relevant solution that get the phy
>    directly without traversing all nodes.
>
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
> ---
>   arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++--------------------
>   1 file changed, 54 insertions(+), 54 deletions(-)
>
> diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
> index 74f2c3d490..6c77f25f23 100644
> --- a/arch/arm/dts/rk3399.dtsi
> +++ b/arch/arm/dts/rk3399.dtsi
> @@ -1387,60 +1387,6 @@
>   			status = "disabled";
>   		};
>   
> -		u2phy0: usb2-phy at e450 {
> -			compatible = "rockchip,rk3399-usb2phy";
> -			reg = <0xe450 0x10>;
> -			clocks = <&cru SCLK_USB2PHY0_REF>;
> -			clock-names = "phyclk";
> -			#clock-cells = <0>;
> -			clock-output-names = "clk_usbphy0_480m";
> -			status = "disabled";
> -
> -			u2phy0_host: host-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "linestate";
> -				status = "disabled";
> -			};
> -
> -			u2phy0_otg: otg-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "otg-bvalid", "otg-id",
> -						  "linestate";
> -				status = "disabled";
> -			};
> -		};
> -
> -		u2phy1: usb2-phy at e460 {
> -			compatible = "rockchip,rk3399-usb2phy";
> -			reg = <0xe460 0x10>;
> -			clocks = <&cru SCLK_USB2PHY1_REF>;
> -			clock-names = "phyclk";
> -			#clock-cells = <0>;
> -			clock-output-names = "clk_usbphy1_480m";
> -			status = "disabled";
> -
> -			u2phy1_host: host-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "linestate";
> -				status = "disabled";
> -			};
> -
> -			u2phy1_otg: otg-port {
> -				#phy-cells = <0>;
> -				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
> -					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> -				interrupt-names = "otg-bvalid", "otg-id",
> -						  "linestate";
> -				status = "disabled";
> -			};
> -		};
> -
>   		emmc_phy: phy at f780 {
>   			compatible = "rockchip,rk3399-emmc-phy";
>   			reg = <0xf780 0x24>;
> @@ -1462,6 +1408,60 @@
>   		};
>   	};
>   
> +	u2phy0: usb2-phy at e450 {
> +		compatible = "rockchip,rk3399-usb2phy";
> +		reg = <0x0 0xe450 0x0 0x10>;
> +		clocks = <&cru SCLK_USB2PHY0_REF>;
> +		clock-names = "phyclk";
> +		#clock-cells = <0>;
> +		clock-output-names = "clk_usbphy0_480m";
> +		status = "disabled";
> +
> +		u2phy0_host: host-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "linestate";
> +			status = "disabled";
> +		};
> +
> +		u2phy0_otg: otg-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "otg-bvalid", "otg-id",
> +					  "linestate";
> +			status = "disabled";
> +		};
> +	};
> +
> +	u2phy1: usb2-phy at e460 {
> +		compatible = "rockchip,rk3399-usb2phy";
> +		reg = <0x0 0xe460 0x0 0x10>;
> +		clocks = <&cru SCLK_USB2PHY1_REF>;
> +		clock-names = "phyclk";
> +		#clock-cells = <0>;
> +		clock-output-names = "clk_usbphy1_480m";
> +		status = "disabled";
> +
> +		u2phy1_host: host-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "linestate";
> +			status = "disabled";
> +		};
> +
> +		u2phy1_otg: otg-port {
> +			#phy-cells = <0>;
> +			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
> +				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "otg-bvalid", "otg-id",
> +					  "linestate";
> +			status = "disabled";
> +		};
> +	};
> +
>   	tcphy0: phy at ff7c0000 {
>   		compatible = "rockchip,rk3399-typec-phy";
>   		reg = <0x0 0xff7c0000 0x0 0x40000>;