[PATCH v5 10/16] usb: dwc3: Enable AutoRetry feature in the controller

Kever Yang kever.yang at rock-chips.com
Fri May 15 04:49:19 CEST 2020


On 2020/5/13 下午3:17, Frank Wang wrote:
> From: Jagan Teki <jagan at amarulasolutions.com>
>
> By default when core sees any transaction error (CRC or overflow) it
> replies with terminating retry ACK (Retry=1 and Nump == 0).
>
> Enabling this Auto Retry feature in controller will make the core send
> a non-terminanting ACK upon such transaction errors. That is, ACK TP
> with Retry=1 and Nump != 0.
>
> Doing so will give controller a chance to recover from transient error
> conditions.
>
> Reference from below Linux commit,
>
> commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
> in the controller")
>
> Cc: Marek Vasut <marex at denx.de>
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/usb/dwc3/core.c | 9 +++++++++
>   drivers/usb/dwc3/core.h | 3 +++
>   2 files changed, 12 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index dc92f471c1..aab6c34c2d 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -995,6 +995,15 @@ int dwc3_init(struct dwc3 *dwc)
>   		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
>   	}
>   
> +	if (dwc->dr_mode == USB_DR_MODE_HOST ||
> +	    dwc->dr_mode == USB_DR_MODE_OTG) {
> +		reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
> +
> +		reg |= DWC3_GUCTL_HSTINAUTORETRY;
> +
> +		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
> +	}
> +
>   	ret = dwc3_core_init_mode(dwc);
>   	if (ret)
>   		goto mode_fail;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index b510d8a983..2adcaf0029 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -160,6 +160,9 @@
>   #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
>   #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
>   
> +/* Global User Control Register */
> +#define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
> +
>   /* Global User Control 1 Register */
>   #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
>   #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)




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