Re: [PATCH v3 2/6] clk: rk3399: Enable/Disable the PCIEPHY clk【请注意，邮件由linux-rockchip-bounces+kever.yang=rock-chips.com at lists.infradead.org代发】

[Kever Yang]

On 2020/5/10 上午12:56, Jagan Teki wrote:
> Enable/Disable the PCIEPHY clk for rk3399.
>
> CLK is clear in both enable and disable functionality.
>
> Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>

Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
> Changes for v3:
> - none
>
>   drivers/clk/rockchip/clk_rk3399.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 5d2bdb42c7..5fb72d83c2 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -1136,6 +1136,9 @@ static int rk3399_clk_enable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_PCIEPHY_REF:
> +		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> +		break;
>   	default:
>   		debug("%s: unsupported clk %ld\n", __func__, clk->id);
>   		return -ENOENT;
> @@ -1209,6 +1212,9 @@ static int rk3399_clk_disable(struct clk *clk)
>   	case HCLK_HOST1_ARB:
>   		rk_setreg(&priv->cru->clksel_con[20], BIT(8));
>   		break;
> +	case SCLK_PCIEPHY_REF:
> +		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
> +		break;
>   	default:
>   		debug("%s: unsupported clk %ld\n", __func__, clk->id);
>   		return -ENOENT;