[PATCH] arm: mach-k3: Enable dcache in SPL
lokeshvutla at ti.com
Tue May 19 11:07:34 CEST 2020
On 19/05/20 12:30 pm, Jan Kiszka wrote:
> On 19.05.20 08:24, Jan Kiszka wrote:
>> On 19.05.20 08:18, Lokesh Vutla wrote:
>>> Hi Jan,
>>> On 18/05/20 11:27 am, Jan Kiszka wrote:
>>>> From: Jan Kiszka <jan.kiszka at siemens.com>
>>>> Add support for enabling dcache already in SPL. It accelerates the boot
>>>> and resolves the risk to run into unaligned 64-bit accesses.
>>>> Based on original patch by Lokesh Vulta.
>>>> Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com>
>>> Thanks for the patch. I guess both R5 SPL and A53 SPL caches gets enabled with
>>> this patch?
>> I strongly suspect so: I didn't find anything in your original patch that
>> prevented that, nor did I add anything in this one.
>> Sorry, I wasn't able to test on an EVM yet, and our target does not use U-Boot
>> for the R5. Would be appreciated if you could throw this on both affected EVMs
>> (of which I only have one anyway).
> Just ran this successfully on the am654-evm.
I was able to boot on J721e-evm as well. Initially I was worried that caches
were not enabled for SRAM when running R5 SPL. But MPU regions are taking care
Acked-by: Lokesh Vutla <lokeshvutla at ti.com>
Will merge this patch soon.
Thanks and regards,
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