[PATCH v4 2/9] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq
sjg at chromium.org
Mon May 25 16:57:28 CEST 2020
On Mon, 25 May 2020 at 05:40, Sylwester Nawrocki <s.nawrocki at samsung.com> wrote:
> There might be hardware configurations where 64-bit data accesses
> to XHCI registers are not supported properly. This patch removes
> the readq/writeq so always two 32-bit accesses are used to read/write
> 64-bit XHCI registers, similarly as it is done in Linux kernel.
> This patch fixes operation of the XHCI controller on RPI4 Broadcom
> BCM2711 SoC based board, where the VL805 USB XHCI controller is
> connected to the PCIe Root Complex, which is attached to the system
> through the SCB bridge.
> Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely
> the 64-bit wide register accesses initiated by the CPU are not properly
> translated to a sequence of 32-bit PCIe accesses.
> xhci_readq(), for example, always returns same value in upper and lower
> 32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234.
> Cc: Sergey Temerkhanov <s.temerkhanov at gmail.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne at suse.de>
> Changes since v1:
> - none.
> Changes since RFC:
> - dropped Kconfig option, switched to not using readq/writeq
> include/usb/xhci.h | 8 --------
> 1 file changed, 8 deletions(-)
Then I think this should be done with a quirk flag, enabled for this
particular device via the compatible string. It should not be an #if,
but an if().
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