[PATCH v12 00/18] RISC-V SiFive FU540 support SPL

[Jagan Teki]

On Tue, May 26, 2020 at 1:35 PM Jagan Teki <jagan at amarulasolutions.com> wrote:
>
> On Mon, May 25, 2020 at 7:52 PM Pragnesh Patel
> <pragnesh.patel at sifive.com> wrote:
> >
> > Hi Bin,
> >
> > >-----Original Message-----
> > >From: Bin Meng <bmeng.cn at gmail.com>
> > >Sent: 25 May 2020 18:42
> > >To: Pragnesh Patel <pragnesh.patel at sifive.com>
> > >Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Atish Patra
> > ><atish.patra at wdc.com>; Palmer Dabbelt <palmerdabbelt at google.com>; Paul
> > >Walmsley <paul.walmsley at sifive.com>; Jagan Teki
> > ><jagan at amarulasolutions.com>; Anup Patel <anup.patel at wdc.com>; Sagar
> > >Kadam <sagar.kadam at sifive.com>; Rick Chen <rick at andestech.com>
> > >Subject: Re: [PATCH v12 00/18] RISC-V SiFive FU540 support SPL
> > >
> > >[External Email] Do not click links or attachments unless you recognize the
> > >sender and know the content is safe
> > >
> > >Hi Pragnesh,
> > >
> > >On Mon, May 25, 2020 at 3:33 PM Pragnesh Patel
> > ><pragnesh.patel at sifive.com> wrote:
> > >>
> > >> This series add support for SPL to FU540. U-Boot SPL can boot from
> > >> L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and
> > >> U-Boot proper from MMC devices.
> > >>
> > >> This series is also available here [1] for testing [1]
> > >> https://github.com/pragnesh26992/u-boot/tree/spl
> > >>
> > >> How to test this patch:
> > >> 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y
> > >> 2) export OPENSBI=<path to
> > >> opensbi/build/platform/generic/firmware/fw_dynamic.bin>
> > >> 3) Change to u-boot-dir
> > >> 4) make sifive_fu540_defconfig
> > >> 5) make all
> > >> 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk
> > >> to switch)
> > >>
> > >>         # sudo sgdisk --clear \
> > >>         > --set-alignment=2 \
> > >>         > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-
> > >FC78-40CD-8002-E86C45580B47 \
> > >>         > --new=2:2082:10273 --change-name=2:loader2 --
> > >typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
> > >>         > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-
> > >8483-4772-8E79-3D69D8477DE4 \
> > >>         > /dev/sda
> > >>
> > >> 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
> > >> 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082
> > >>
> > >> Changes in v12:
> > >> - Rebase on mainline U-Boot
> > >>   Added necessary include files which are not part of common header now
> > >>   Remove unnecessary include files
> > >>
> > >>   drivers/misc/sifive-otp.c
> > >>         +#include <linux/bitops.h>
> > >>         +#include <linux/delay.h>
> > >>
> > >>   board/sifive/fu540/fu540.c
> > >>         -#include <common.h>
> > >>         +#include <log.h>
> > >>
> > >>   board/sifive/fu540/spl.c
> > >>         +#include <init.h>
> > >>         +#include <log.h>
> > >>         +#include <linux/delay.h>
> > >>
> > >>   drivers/ram/sifive/fu540_ddr.c
> > >>         +#include <linux/bitops.h>
> > >>
> > >>   arch/riscv/cpu/fu540/cpu.c
> > >>         -#include <common.h>
> > >>         +#include <asm/cache.h>
> > >>
> > >>   arch/riscv/cpu/fu540/spl.c
> > >>         -#include <common.h>
> > >>         +#include <log.h>
> > >>
> > >>   board/sifive/fu540/spl.c
> > >>         -#include <common.h>
> > >>         +#include <init.h>
> > >>         +#include <log.h>
> > >>         +#include <linux/delay.h>
> > >>
> > >> - Update commit description for Release ethernet clock reset
> > >> - Update OpenSBI building section in "doc/board/sifive/fu540.rst"
> > >>
> > >
> > >Thanks. During the testing I found there is one issue about ethernet.
> > >
> > >The 1000Mbps does not work. Only 100Mbps works. Could you please have a
> > >look?
> >
> > Yes, you are right. This is because ethernet clock rate is not setting properly.
> >
> > FSBL set the ethernet clock rate to 125 Mhz.
> > https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/main.c#L256
> >
> >
> > U-Boot can do the same with below lines:
> >
> > eth0: ethernet at 10090000 {
> >         +assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
> >         +assigned-clock-rates = <125000000>;
> > };
> >
> > I will update this in v13, thanks for the testing.
>
> Please share your latest version, I will update the partition table.

Sorry for making noise, yes we agreed to have separate partition
tables for SD and SPI.

Jagan.