[PATCH v2 00/12] mips: Add initial Octeon MIPS64 base support

[Stefan Roese]

Hi Daniel,

On 14.05.20 11:59, Stefan Roese wrote:
> 
> This patch adds very basic support for the Octeon III SoCs. Only CFI
> parallel UART, reset and NOR flash are supported for now.
> 
> Please note that the basic Octeon port does not include the DDR3/4
> initialization yet. This will be added in some follow-up patches later.
> To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III
> CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such
> boards.
> 
> Thanks,
> Stefan
> 
> Changes in v2:
> - New patch
> - New patch
> - Restructure patch by adding empty functions to asm/cm.h instead
> - New patch
> - New patch
> - Move bit macro definition to mipsregs.h
> - Remove custom start.S and use common start.S. Minimal custom lowlevel
>    init code is currently added in the custom lowlevel_init.S. This needs
>    to be extended with necessary code, like errata handling etc. But for
>    a very first basic port, this seems to be all thats needed to boot on
>    the EBB7304 to the prompt.
> - Removed select CREATE_ARCH_SYMLINK
> - Removed Octeon II support, as its currently no added in this patchset
> - Added cache.c to add the platform specific cache functions as no-ops
>    for Octeon as the platform is cache coherent
> - Removed CONFIG_MIPS_CACHE_COHERENT
> - Added CONFIG_CPU_CAVIUM_OCTEON to Kconfig and selected it for Octeon
>    to enable better sync with the Linux files in the future
> - Add get_tbclk() -> no need to define CONFIG_SYS_MIPS_TIMER_FREQ any more
> - Removed CONFIG_SYS_MIPS_TIMER_FREQ

Daniel, do you have any comments and / or change requests to v2 of this
base Octeon patchset?

Thanks,
Stefan