[PATCH 2/2] mv_ddr: ddr3: Update {min, max}_read_sample calculation

[Baruch Siach]

Hi Chris,

On Wed, May 27 2020, Chris Packham wrote:

> From: Chris Packham <chris.packham at alliedtelesis.co.nz>
>
> Measurements on actual hardware shown that the read ODT is early by 3
> clocks. Adjust the calculation to avoid this.
>
> Signed-off-by: Chris Packham <chris.packham at alliedtelesis.co.nz>
>
> [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
> Signed-off-by: Chris Packham <judge.packham at gmail.com>

Tested here on an Armada 385 based system. Running memtester for more
than an hour.

Tested-by: Baruch Siach <baruch at tkos.co.il>

Thanks,
baruch

> ---
>
>  drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> index ce9a47fc2ce0..58ffb205072e 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
>  			min_read_sample = read_sample[cs_num];
>  	}
>  
> -	min_read_sample = min_read_sample - 1;
> -	max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
> +	min_read_sample = min_read_sample + 2;
> +	max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1;
>  	if (min_read_sample >= 0xf)
>  		min_read_sample = 0xf;
>  	if (max_read_sample >= 0x1f)


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