[PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu features

[Pragnesh Patel]

Hi Sagar,

>-----Original Message-----
>From: Sagar Kadam <sagar.kadam at sifive.com>
>Sent: 26 May 2020 22:39
>To: u-boot at lists.denx.de; rick at andestech.com; lukma at denx.de
>Cc: jagan at amarulasolutions.com; bmeng.cn at gmail.com; Pragnesh Patel
><pragnesh.patel at sifive.com>; seanga2 at gmail.com; Sagar Kadam
><sagar.kadam at sifive.com>
>Subject: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu features
>
>All cpu cores within FU540-C000 having split I/D caches.
>Set the L1 feature bit using the i-cache-size as one of the property from

s/L1 feature/L1 cache feature

>device tree indicating that L1 cache is present on the cpu core.
>
>=> cpu detail
>  0: cpu at 0      rv64imac
>        ID = 0, freq = 999.100 MHz: L1 cache
>  1: cpu at 1      rv64imafdc
>        ID = 1, freq = 999.100 MHz: L1 cache, MMU
>  2: cpu at 2      rv64imafdc
>        ID = 2, freq = 999.100 MHz: L1 cache, MMU
>  3: cpu at 3      rv64imafdc
>        ID = 3, freq = 999.100 MHz: L1 cache, MMU
>  4: cpu at 4      rv64imafdc
>        ID = 4, freq = 999.100 MHz: L1 cache, MMU
>
>Signed-off-by: Sagar Shrikant Kadam <sagar.kadam at sifive.com>

Reviewed-by: Pragnesh Patel <Pragnesh.patel at sifive.com>