[PATCH 0/2] Enable all cache ways and Enable SiFive PWM driver

Pragnesh Patel pragnesh.patel at sifive.com
Fri May 29 08:44:50 CEST 2020

Patch 1: enable all cache ways from U-Boot proper

This patch enables all cache ways from U-Boot proper, earlier this was
done by FSBL.

L2 cache is of 2 MB (16 cache ways) and 1 cache way is of 128 KB.
FSBL is located on the latest way of L2 cache. Therefore, FSBL can
only enable the first 15 L2 cache ways to avoid corrupt itself.

U-Boot proper enables all cache ways (16 cache ways) in this patch.

Patch 2: Enable SiFive PWM driver

This patch enables SiFive PWM driver for the SiFive Unleashed board.

This series is rebase on 
- [v13] RISC-V SiFive FU540 support SPL

This series depends on:
[1] https://patchwork.ozlabs.org/patch/1275883

All these together is available for testing here
[2] https://github.com/pragnesh26992/u-boot/tree/pwm

Pragnesh Patel (2):
  riscv: sifive: fu540: enable all cache ways from U-Boot proper
  riscv: sifive: fu540: Enable SiFive PWM driver

 arch/riscv/cpu/fu540/Makefile             |  1 +
 arch/riscv/cpu/fu540/cache.c              | 53 +++++++++++++++++++++++
 arch/riscv/dts/fu540-c000-u-boot.dtsi     |  4 ++
 arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++
 board/sifive/fu540/Kconfig                |  2 +
 board/sifive/fu540/fu540.c                | 10 ++++-
 6 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/cpu/fu540/cache.c
 create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h


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