[PATCH 1/2] riscv: sifive: fu540: enable all cache ways from U-Boot proper

[Bin Meng]

On Fri, May 29, 2020 at 2:45 PM Pragnesh Patel
<pragnesh.patel at sifive.com> wrote:
>
> Add L2 cache node to enable all cache ways from U-Boot proper.
>
> Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>  arch/riscv/cpu/fu540/Makefile             |  1 +
>  arch/riscv/cpu/fu540/cache.c              | 53 +++++++++++++++++++++++
>  arch/riscv/dts/fu540-c000-u-boot.dtsi     |  4 ++
>  arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++
>  board/sifive/fu540/fu540.c                | 10 ++++-
>  5 files changed, 81 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/cpu/fu540/cache.c
>  create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h
>

Tested-by: Bin Meng <bmeng.cn at gmail.com>