[PATCH 19/26] arm: mach-k3: j721e: force enable A72 core 0 during spl shutdown

[Tero Kristo]

On 16/11/2020 06:21, Lokesh Vutla wrote:
> 
> 
> On 10/11/20 2:35 pm, Tero Kristo wrote:
>> With the new raw register mode access PM drivers, A72 core is not
>> enabled via ti-sci services, leading into bad usecounts for the core.
>> This effectively shuts down the A72 core when SPL goes down. Prevent the
> 
> When you meant SPL that is R5 going down correct?. But in this case R5 can never
> go down no? I am still trying to understand what happens if this patch is not
> applied.
> 
> Is it that R5 gets reset before jumping to DM firmware? Also at this point DM
> services are not available no? who services this get_device request?

This does not touch R5 as you see from the code, the device ID touched 
is A72SS0. Basically what happens is that A72 is booted directly by R5 
SPL, but once u-boot shutdown services kick in, they terminate A72 
power-domain because it is no longer used by any of the device drivers. 
Sysfw usecount is increased by A72 ATF, which keeps the core enabled in 
pure sysfw case, but our R5 SPL drivers do not have this info so they 
terminate it forcibly.

However, this might not be needed at all in the latest version of the 
code, as we always start a firmware image on MCU R5 and the 
release_resources_for_core_shutdown never gets called. Let me retry this 
once I re-spin this series.

-Tero

> 
> Thanks and regards,
> Lokesh
> 
>> problem by force enabling the A72 core once, which increases the use
>> count.
>>
>> Signed-off-by: Tero Kristo <t-kristo at ti.com>
>> ---
>>   arch/arm/mach-k3/j721e_init.c | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
>> index a36e4ed603..d00a9477a2 100644
>> --- a/arch/arm/mach-k3/j721e_init.c
>> +++ b/arch/arm/mach-k3/j721e_init.c
>> @@ -306,6 +306,7 @@ u32 spl_boot_device(void)
>>   
>>   #ifdef CONFIG_SYS_K3_SPL_ATF
>>   
>> +#define J721E_DEV_A72SS0_CORE0			202
>>   #define J721E_DEV_MCU_RTI0			262
>>   #define J721E_DEV_MCU_RTI1			263
>>   #define J721E_DEV_MCU_ARMSS0_CPU0		250
>> @@ -324,10 +325,23 @@ void release_resources_for_core_shutdown(void)
>>   		J721E_DEV_MCU_RTI1,
>>   	};
>>   
>> +	const u32 get_device_ids[] = {
>> +		J721E_DEV_A72SS0_CORE0
>> +	};
>> +
>>   	ti_sci = get_ti_sci_handle();
>>   	dev_ops = &ti_sci->ops.dev_ops;
>>   	proc_ops = &ti_sci->ops.proc_ops;
>>   
>> +	/* Iterate through list of devices to get (enable) */
>> +	for (i = 0; i < ARRAY_SIZE(get_device_ids); i++) {
>> +		u32 id = get_device_ids[i];
>> +
>> +		ret = dev_ops->get_device(ti_sci, id);
>> +		if (ret)
>> +			panic("Failed to get device %u (%d)\n", id, ret);
>> +	}
>> +
>>   	/* Iterate through list of devices to put (shutdown) */
>>   	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
>>   		u32 id = put_device_ids[i];
>>

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