[PATCH 4/4] arm64: zynqmp: Enable FPGA loading from SPL

[Michal Simek]

fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.

Signed-off-by: Michal Simek <michal.simek at xilinx.com>
---

 configs/xilinx_zynqmp_virt_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index c54ddffdd6f3..79a0091b1981 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -21,6 +21,7 @@ CONFIG_USE_PREBOOT=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_FPGA=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
-- 
2.28.0