[Uboot-stm32] [PATCH 0/7] arm: cache: cp15: don't map reserved region with no-map property

[Patrick DELAUNAY]

Hi Ahmad,

> From: Ahmad Fatoum <a.fatoum at pengutronix.de>
> Sent: mercredi 7 octobre 2020 13:24
> 
> Hello Ard, Patrick,
> 
> On 10/7/20 12:26 PM, Ard Biesheuvel wrote:
> >> The issue is solved only when the region reserved by OP-TEE is no
> >> more mapped in U-Boot (mapped as DEVICE/NON-CACHEABLE wasn't
> enough)
> >> as it is already done in Linux kernel.
> >>
> >
> > Spurious peculative accesses to device regions would be a severe
> > silicon bug, so I wonder what is going on here.
> >
> > (Apologies if we are rehashing stuff here that has already been
> > discussed - I don't remember the details)
> >
> > Are you sure that the speculative accesses were not caused by
> > misconfigured CPU or page tables, missing TLB maintenance, etc etc?
> > Because it really does smell like a software issue not a hardware
> > issue.
> 
> I debugged a similar issue a year ago on an i.MX6 UltraLite (also a Cortex-A7)
> that turned to ultimately be caused by barebox not mapping I/O memory as non-
> executable. This led to very interesting effects.
> 
> My findings[1] back then were that U-Boot did set the eXecute Never bit only on
> OMAP, but not for other platforms.  So I could imagine this being the root cause of
> Patrick's issues as well:
> The CPU is speculatively executing from the region that the firewalled DRAM is
> mapped at.
> 
> barebox now configures XN for non-RAM before it turns on the MMU. You should
> do that as well (in ARM arch code, not only for stm32mp1). Additionally, you will
> want to XN map the region where your OP-TEE sits at.
> 
> [1]: https://community.nxp.com/thread/511925

Thanks to point me this thread.

I checked DACR behavior and CheckDomain /  CheckPermission

In my case the cortex A7 try to access to part of DDR / mapped cacheable and bufferable, protected by firewall.

So to use DACR I always need to configure the MMU with several Domain
- unsecure part of DDR as Domain 0 (DCACHE_WRITEALLOC)
- secure part of DDR as  Domain 1 (DCACHE_OFF)

For other part of MMU region, the I/O registers are mapped as register with Domain 0 (D_CACHE_OFF)

Then I can set DACR = 0x55555555
=> Client Accesses are checked against the access permission bits in the TLB entry

You ar right, the access permission is check only for domain configurated as client in DACR

But in ARM architecture

B2.4.8 Access permission checking

CheckPermission() pseudo code
Only check perms.ap is checked
And perms.xp is not checked 

But as the secure memory is mapped cacheable by secure OS, OP-TEE
I think to avoid to map the region is the ARM preconized solution
As explain in my answer to ard in [1]

[1] http://u-boot.10912.n7.nabble.com/PATCH-0-7-arm-cache-cp15-don-t-map-reserved-region-with-no-map-property-tt428715.html#a428958
 
> Cheers
> Ahmad
> 
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