[PATCH 2/3] phy: marvell: cp110: let the firmware configure comphy for PCIe
Baruch Siach
baruch at tkos.co.il
Sun Oct 18 16:11:12 CEST 2020
From: Grzegorz Jaszczyk <jaz at semihalf.com>
Replace the comphy initialization for PCIe with appropriate SMC call, so
the firmware will perform appropriate comphy initialization.
Signed-off-by: Grzegorz Jaszczyk <jaz at semihalf.com>
Signed-off-by: Ken Ma <make at marvell.com>
Reviewed-by: Igal Liberman <igall at marvell.com>
Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
drivers/phy/marvell/comphy_cp110.c | 451 +----------------------------
1 file changed, 12 insertions(+), 439 deletions(-)
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 31baa0bb3700..5b6aaa62487b 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -31,6 +31,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12)
#define COMPHY_FW_FORMAT(mode, idx, speeds) \
(((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
+
+#define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \
+ (((pcie_width) << 18) | ((clk_src) << 17) | \
+ COMPHY_FW_FORMAT(mode, 0, speeds))
+
#define COMPHY_SATA_MODE 0x1
#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
@@ -112,441 +117,6 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val,
return 0;
}
-static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
- bool is_end_point, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
- u32 pcie_clk = 0; /* set input by default */
-
- debug_enter();
-
- /*
- * ToDo:
- * Add SAR (Sample-At-Reset) configuration for the PCIe clock
- * direction. SAR code is currently not ported from Marvell
- * U-Boot to mainline version.
- *
- * SerDes Lane 4/5 got the PCIe ref-clock #1,
- * and SerDes Lane 0 got PCIe ref-clock #0
- */
- debug("PCIe clock = %x\n", pcie_clk);
- debug("PCIe RC = %d\n", !is_end_point);
- debug("PCIe width = %d\n", pcie_width);
-
- /* enable PCIe by4 and by2 */
- if (lane == 0) {
- if (pcie_width == 4) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
- COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
- } else if (pcie_width == 2) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
- COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
- }
- }
-
- /*
- * If PCIe clock is output and clock source from SerDes lane 5,
- * we need to configure the clock-source MUX.
- * By default, the clock source is from lane 4
- */
- if (pcie_clk && clk_src && (lane == 5)) {
- reg_set((void __iomem *)DFX_DEV_GEN_CTRL12,
- 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET,
- DFX_DEV_GEN_PCIE_CLK_SRC_MASK);
- }
-
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- mask |= COMMON_PHY_PHY_MODE_MASK;
- data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* release from hard reset */
- mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* Set PIPE soft reset */
- mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
- data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
- /* Set PHY datapath width mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
- data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
- /* Set Data bus width USB mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
- /* Set CORE_CLK output frequency for 250Mhz */
- mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
- /* Set PLL ready delay for 0x2 */
- data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
- mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
- if (pcie_width != 1) {
- data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
- mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
- data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
- mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
- }
- reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
-
- /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */
- data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
- mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
- if (pcie_width != 1) {
- mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
- mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
- mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
- if (lane == 0) {
- data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
- data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
- } else if (lane == (pcie_width - 1)) {
- data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
- }
- }
- reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
- /* Config update polarity equalization */
- reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG,
- 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET,
- HPIPE_CFG_UPDATE_POLARITY_MASK);
- /* Set PIPE version 4 to mode enable */
- reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG,
- 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET,
- HPIPE_DFE_CTRL_28_PIPE4_MASK);
- /* TODO: check if pcie clock is output/input - for bringup use input*/
- /* Enable PIN clock 100M_125M */
- mask = 0;
- data = 0;
- /* Only if clock is output, configure the clock-source mux */
- if (pcie_clk) {
- mask |= HPIPE_MISC_CLK100M_125M_MASK;
- data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
- }
- /*
- * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz
- * clock
- */
- mask |= HPIPE_MISC_TXDCLK_2X_MASK;
- data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
- /* Enable 500MHz Clock */
- mask |= HPIPE_MISC_CLK500_EN_MASK;
- data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
- if (pcie_clk) { /* output */
- /* Set reference clock comes from group 1 */
- mask |= HPIPE_MISC_REFCLK_SEL_MASK;
- data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
- } else {
- /* Set reference clock comes from group 2 */
- mask |= HPIPE_MISC_REFCLK_SEL_MASK;
- data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
- }
- mask |= HPIPE_MISC_ICP_FORCE_MASK;
- data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
- reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
- if (pcie_clk) { /* output */
- /* Set reference frequcency select - 0x2 for 25MHz*/
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- } else {
- /* Set reference frequcency select - 0x0 for 100MHz*/
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- }
- /* Set PHY mode to PCIe */
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
-
- /* ref clock alignment */
- if (pcie_width != 1) {
- mask = HPIPE_LANE_ALIGN_OFF_MASK;
- data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
- }
-
- /*
- * Set the amount of time spent in the LoZ state - set for 0x7 only if
- * the PCIe clock is output
- */
- if (pcie_clk) {
- reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
- 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
- HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
- }
-
- /* Set Maximal PHY Generation Setting(8Gbps) */
- mask = HPIPE_INTERFACE_GEN_MAX_MASK;
- data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
- /* Bypass frame detection and sync detection for RX DATA */
- mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
- data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
- /* Set Link Train Mode (Tx training control pins are used) */
- mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
- data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
- reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
-
- /* Set Idle_sync enable */
- mask = HPIPE_PCIE_IDLE_SYNC_MASK;
- data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
- /* Select bits for PCIE Gen3(32bit) */
- mask |= HPIPE_PCIE_SEL_BITS_MASK;
- data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
- reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
-
- /* Enable Tx_adapt_g1 */
- mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
- data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
- /* Enable Tx_adapt_gn1 */
- mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
- data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
- /* Disable Tx_adapt_g0 */
- mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
- data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
- reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
-
- /* Set reg_tx_train_chk_init */
- mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
- data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
- /* Enable TX_COE_FM_PIN_PCIE3_EN */
- mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
- data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
- reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
-
- debug("stage: TRx training parameters\n");
- /* Set Preset sweep configurations */
- mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
- data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
-
- mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
- data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
-
- mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
- data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
-
- /* Tx train start configuration */
- mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
- data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
-
- mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
- data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
-
- mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
- data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
-
- mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
- data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
-
- /* Enable Tx train P2P */
- mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
- data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
- reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
-
- /* Configure Tx train timeout */
- mask = HPIPE_TRX_TRAIN_TIMER_MASK;
- data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
- reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
-
- /* Disable G0/G1/GN1 adaptation */
- mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
- | HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
- data = 0;
- reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
-
- /* Disable DTL frequency loop */
- mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
- data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
-
- /* Configure G3 DFE */
- mask = HPIPE_G3_DFE_RES_MASK;
- data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
- reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
-
- /* Use TX/RX training result for DFE */
- mask = HPIPE_DFE_RES_FORCE_MASK;
- data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
- reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
-
- /* Configure initial and final coefficient value for receiver */
- mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
- data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
-
- mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
- data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
-
- mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
- data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
-
- /* Trigger sampler enable pulse */
- mask = HPIPE_SMAPLER_MASK;
- data = 0x1 << HPIPE_SMAPLER_OFFSET;
- reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
- udelay(5);
- reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
-
- /* FFE resistor tuning for different bandwidth */
- mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
- data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
-
- mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
- data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
-
- /* Pattern lock lost timeout disable */
- mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
- data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
-
- /* Configure DFE adaptations */
- mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
- data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
- mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
- data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
- mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
- data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
- reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
- mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
- data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
- reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
-
- /* Genration 2 setting 1*/
- mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
- data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
- mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
- data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
- reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
-
- /* DFE enable */
- mask = HPIPE_G2_DFE_RES_MASK;
- data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
- reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
-
- /* Configure DFE Resolution */
- mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
- data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
-
- /* VDD calibration control */
- mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
- data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
- reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
-
- /* Set PLL Charge-pump Current Control */
- mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
- data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
- reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
-
- /* Set lane rqualization remote setting */
- mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
- data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
- mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
- data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
- mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
- data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
-
- if (!is_end_point) {
- /* Set phy in root complex mode */
- mask = HPIPE_CFG_PHY_RC_EP_MASK;
- data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
- }
-
- debug("stage: Comphy power up\n");
-
- /*
- * For PCIe by4 or by2 - release from reset only after finish to
- * configure all lanes
- */
- if ((pcie_width == 1) || (lane == (pcie_width - 1))) {
- u32 i, start_lane, end_lane;
-
- if (pcie_width != 1) {
- /* allows writing to all lanes in one write */
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x0 <<
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
- start_lane = 0;
- end_lane = pcie_width;
-
- /*
- * Release from PIPE soft reset
- * for PCIe by4 or by2 - release from soft reset
- * all lanes - can't use read modify write
- */
- reg_set(HPIPE_ADDR(hpipe_base, 0) +
- HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff);
- } else {
- start_lane = lane;
- end_lane = lane + 1;
-
- /*
- * Release from PIPE soft reset
- * for PCIe by4 or by2 - release from soft reset
- * all lanes
- */
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
- }
-
-
- if (pcie_width != 1) {
- /* disable writing to all lanes with one write */
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x3210 <<
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
- COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
- }
-
- debug("stage: Check PLL\n");
- /* Read lane status */
- for (i = start_lane; i < end_lane; i++) {
- addr = HPIPE_ADDR(hpipe_base, i) +
- HPIPE_LANE_STATUS1_REG;
- data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- hpipe_addr + HPIPE_LANE_STATUS1_REG,
- data);
- pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
- ret = 0;
- }
- }
- }
-
- debug_exit();
- return ret;
-}
-
static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
void __iomem *comphy_base)
{
@@ -1346,10 +916,13 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
case PHY_TYPE_PEX1:
case PHY_TYPE_PEX2:
case PHY_TYPE_PEX3:
- ret = comphy_pcie_power_up(
- lane, pcie_width, ptr_comphy_map->clk_src,
- serdes_map->end_point,
- hpipe_base_addr, comphy_base_addr);
+ mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
+ ptr_comphy_map->clk_src,
+ COMPHY_PCIE_MODE,
+ ptr_comphy_map->speed);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane,
+ mode);
break;
case PHY_TYPE_SATA0:
case PHY_TYPE_SATA1:
--
2.28.0
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