[PATCH v2] serial: pl01x: Add error value checking

[Michal Simek]

po 19. 10. 2020 v 16:08 odesílatel Michal Simek
<michal.simek at xilinx.com> napsal:
>
> There also a need to check return values to make sure that clocks were
> enabled and setup properly.
>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> Reviewed-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v2:
> - Add missing header
> - Add Simon's tag
>
>  drivers/serial/serial_pl01x.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
> index 2772c25f1d2d..d9e35c6a2b47 100644
> --- a/drivers/serial/serial_pl01x.c
> +++ b/drivers/serial/serial_pl01x.c
> @@ -19,6 +19,7 @@
>  #include <watchdog.h>
>  #include <asm/io.h>
>  #include <serial.h>
> +#include <dm/device_compat.h>
>  #include <dm/platform_data/serial_pl01x.h>
>  #include <linux/compiler.h>
>  #include "serial_pl01x_internal.h"
> @@ -362,8 +363,18 @@ int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
>         plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
>         ret = clk_get_by_index(dev, 0, &clk);
>         if (!ret) {
> -               clk_enable(&clk);
> +               ret = clk_enable(&clk);
> +               if (ret && ret != -ENOSYS) {
> +                       dev_err(dev, "failed to enable clock\n");
> +                       return ret;
> +               }
> +
>                 plat->clock = clk_get_rate(&clk);
> +               if (IS_ERR_VALUE(plat->clock)) {
> +                       dev_err(dev, "failed to get rate\n");
> +                       return plat->clock;
> +               }
> +               debug("%s: CLK %d\n", __func__, plat->clock);
>         }
>         plat->type = dev_get_driver_data(dev);
>         plat->skip_init = dev_read_bool(dev, "skip-init");
> --
> 2.28.0
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
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