[PATCH v2] spi: zynq_qspi: Use clk subsystem to get reference qspi clk

[Michal Simek]

po 19. 10. 2020 v 16:09 odesílatel Michal Simek
<michal.simek at xilinx.com> napsal:
>
> From: T Karthik Reddy <t.karthik.reddy at xilinx.com>
>
> Remove fixed reference clk used by plat->frequency and use clk
> subsystem to get reference clk. As per spi dt bindings
> "spi-max-frequency" property should be used by the slave devices.
> This property is read by spi-uclass driver for the slave device.
> So avoid reading above property from the platform driver.
>
> Signed-off-by: T Karthik Reddy <t.karthik.reddy at xilinx.com>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> ---
>
> Changes in v2:
> - Fix dev_err message first parameter and add missing header
>
>  drivers/spi/zynq_qspi.c | 36 ++++++++++++++++++++++++++++--------
>  1 file changed, 28 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
> index 3f39ef05f2d6..4219a35c8406 100644
> --- a/drivers/spi/zynq_qspi.c
> +++ b/drivers/spi/zynq_qspi.c
> @@ -6,8 +6,10 @@
>   * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
>   */
>
> +#include <clk.h>
>  #include <common.h>
>  #include <dm.h>
> +#include <dm/device_compat.h>
>  #include <log.h>
>  #include <malloc.h>
>  #include <spi.h>
> @@ -105,14 +107,6 @@ static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
>         plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
>                                                               node, "reg");
>
> -       /* FIXME: Use 166MHz as a suitable default */
> -       plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
> -                                       166666666);
> -       plat->speed_hz = plat->frequency / 2;
> -
> -       debug("%s: regs=%p max-frequency=%d\n", __func__,
> -             plat->regs, plat->frequency);
> -
>         return 0;
>  }
>
> @@ -159,13 +153,39 @@ static int zynq_qspi_probe(struct udevice *bus)
>  {
>         struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
>         struct zynq_qspi_priv *priv = dev_get_priv(bus);
> +       struct clk clk;
> +       unsigned long clock;
> +       int ret;
>
>         priv->regs = plat->regs;
>         priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
>
> +       ret = clk_get_by_name(bus, "ref_clk", &clk);
> +       if (ret < 0) {
> +               dev_err(bus, "failed to get clock\n");
> +               return ret;
> +       }
> +
> +       clock = clk_get_rate(&clk);
> +       if (IS_ERR_VALUE(clock)) {
> +               dev_err(bus, "failed to get rate\n");
> +               return clock;
> +       }
> +
> +       ret = clk_enable(&clk);
> +       if (ret && ret != -ENOSYS) {
> +               dev_err(bus, "failed to enable clock\n");
> +               return ret;
> +       }
> +
>         /* init the zynq spi hw */
>         zynq_qspi_init_hw(priv);
>
> +       plat->frequency = clock;
> +       plat->speed_hz = plat->frequency / 2;
> +
> +       debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
> +
>         return 0;
>  }
>
> --
> 2.28.0
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs