[PATCH 1/5 v2] mips: start.S: Add Octeon boot header compatibility

[Stefan Roese]

Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC.
Here the only 2 instructions are allowed in the first few bytes of the
image. And these instructions need to be one branch and a nop. This
patch adds the necessary nop after the nop, to that the common MIPS
image is compatible with this Octeon header.

The tool to patch the Octeon boot header into the image will be send in
a follow-up patch.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Aaron Williams <awilliams at marvell.com>
Cc: Chandrakala Chavva <cchavva at marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>
---
v2:
- Enhance comment
- Fix delay slot indentation

 arch/mips/cpu/start.S | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index d0c412236d..335aafa6a8 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -74,9 +74,14 @@
 	.endm
 
 ENTRY(_start)
-	/* U-Boot entry point */
+	/*
+	 * U-Boot entry point.
+	 * Do not add instructions to the branch delay slot! Some SoC's
+	 * like Octeon might patch the final U-Boot binary at this location
+	 * with additional boot headers.
+	 */
 	b	reset
-	 mtc0	zero, CP0_COUNT	# clear cp0 count for most accurate boot timing
+	 nop
 
 #if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
 	/*
@@ -123,6 +128,7 @@ ENTRY(_start)
 #endif
 
 reset:
+	mtc0	zero, CP0_COUNT	# clear cp0 count for most accurate boot timing
 #if __mips_isa_rev >= 6
 	mfc0	t0, CP0_CONFIG, 5
 	and	t0, t0, MIPS_CONF5_VP
-- 
2.29.1