[PATCH 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
Meenakshi Aggarwal
meenakshi.aggarwal at nxp.com
Wed Sep 2 11:59:22 CEST 2020
> -----Original Message-----
> From: Priyanka Jain <priyanka.jain at nxp.com>
> Sent: Wednesday, September 2, 2020 12:49 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>; u-
> boot at lists.denx.de
> Cc: Varun Sethi <V.Sethi at nxp.com>
> Subject: RE: [PATCH 1/2] armv8: lx2162a: Add Soc changes to support
> LX2162A
>
>
>
> >-----Original Message-----
> >From: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
> >Sent: Tuesday, September 1, 2020 3:03 PM
> >To: u-boot at lists.denx.de; Priyanka Jain <priyanka.jain at nxp.com>
> >Cc: Varun Sethi <V.Sethi at nxp.com>; Meenakshi Aggarwal
> ><meenakshi.aggarwal at nxp.com>
> >Subject: [PATCH 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
> >
> >From: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
> >
> >LX2162 is LX2160 based SoC, it has same die as of LX2160 with different
> >packaging.
> >LX2162A support 4GB ddr memory, i2c, micro-click module, microSD card,
> >serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
> >interface,one usb 3.0 and serdes interface to support three x1 gen3
> >pcie interface.
> Are these Soc features or board features, please check. Similar description is
> used for both Soc and board patch
> >
> >Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal at nxp.com>
> >---
> > arch/arm/cpu/armv8/Kconfig | 2 +-
> > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++-
> > arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19
> >++++++++++++++++++-
> > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 5 ++++-
> > drivers/pci/pcie_layerscape_ep.c | 4 +++-
> > drivers/pci/pcie_layerscape_fixup_common.c | 5 ++++-
> > 6 files changed, 34 insertions(+), 6 deletions(-)
> >
> >diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> >index 3655990..f247441 100644
> >--- a/arch/arm/cpu/armv8/Kconfig
> >+++ b/arch/arm/cpu/armv8/Kconfig
> >@@ -115,7 +115,7 @@ config PSCI_RESET
> > !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
> > !TARGET_LS1046AFRWY && \
> > !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
> >- !TARGET_LX2160AQDS && \
> >+ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
> > !ARCH_UNIPHIER && !TARGET_S32V234EVB
> > help
> > Most armv8 systems have PSCI support enabled in EL3, either
> through
> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >index 8a2f404..4fb222a 100644
> >--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >@@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> >- * Copyright 2017-2019 NXP
> >+ * Copyright 2017-2020 NXP
> > * Copyright 2014-2015 Freescale Semiconductor, Inc.
> > */
> >
> >@@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
> > CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
> > CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
> > CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
> >+ CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
> >+ CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
> >+ CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
> > };
> >
> > #define EARLY_PGTABLE_SIZE 0x5000
> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >index a04a370..b4dea80 100644
> >--- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >@@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> >- * Copyright 2018 NXP
> >+ * Copyright 2018, 2020 NXP
> > */
> >
> > #include <common.h>
> >@@ -11,6 +11,22 @@ struct serdes_config {
> > u8 lanes[SRDS_MAX_LANES];
> > };
> >
> >+#ifdef CONFIG_TARGET_LX2162AQDS
> Board change
These are SoC changes but as LX2162 is LX2160 bases so I didn't define a separate config for LX2162A,
Rather used CONFIG_TARGET_LX2162AQDS.
Suggest if I should define one for LX2162A SOC?
> >+static struct serdes_config serdes1_cfg_tbl[] = {
> >+ /* SerDes 1 */
> >+ {0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> >+ {0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
> >+ {0x03, {XFI6, XFI5, XFI4, XFI3 } },
> >+ {0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
> >+ {0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
> >+ {0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
> >+ {0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
> >+ {0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
> >+ {0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
> >+ {0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
> >+ {}
> >+};
> >+#else
> > static struct serdes_config serdes1_cfg_tbl[] = {
> > /* SerDes 1 */
> > {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
> >@@ -
> >48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
> > {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
> > {}
> > };
> >+#endif
> >
> > static struct serdes_config serdes2_cfg_tbl[] = {
> > /* SerDes 2 */
> >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >index 020548a..cbca43f 100644
> >--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
> >@@ -1,6 +1,6 @@
> > /* SPDX-License-Identifier: GPL-2.0+ */
> > /*
> >- * Copyright 2017-2019 NXP
> >+ * Copyright 2017-2020 NXP
> > * Copyright 2015 Freescale Semiconductor */
> >
> >@@ -106,6 +106,9 @@ enum boot_src get_boot_src(void);
> > #define SVR_LX2160A 0x873600
> > #define SVR_LX2120A 0x873620
> > #define SVR_LX2080A 0x873602
> >+#define SVR_LX2162A 0x873608
> >+#define SVR_LX2122A 0x873628
> >+#define SVR_LX2082A 0x87360A
> >
> > #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
> > #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
> >diff --git a/drivers/pci/pcie_layerscape_ep.c
> >b/drivers/pci/pcie_layerscape_ep.c
> >index eba230e..fd26ff7 100644
> >--- a/drivers/pci/pcie_layerscape_ep.c
> >+++ b/drivers/pci/pcie_layerscape_ep.c
> >@@ -272,7 +272,9 @@ static int ls_pcie_ep_probe(struct udevice *dev)
> >
> > svr = SVR_SOC_VER(get_svr());
> >
> >- if (svr == SVR_LX2160A)
> >+ if (svr == SVR_LX2160A || svr == SVR_LX2162A ||
> >+ svr == SVR_LX2120A || svr == SVR_LX2080A ||
> >+ svr == SVR_LX2122A || svr == SVR_LX2082A)
> > pcie_ep->pf1_offset = LX2160_PCIE_PF1_OFFSET;
> > else
> > pcie_ep->pf1_offset = LS_PCIE_PF1_OFFSET; diff --git
> >a/drivers/pci/pcie_layerscape_fixup_common.c
> >b/drivers/pci/pcie_layerscape_fixup_common.c
> >index fef0a75..8a2228c 100644
> >--- a/drivers/pci/pcie_layerscape_fixup_common.c
> >+++ b/drivers/pci/pcie_layerscape_fixup_common.c
> >@@ -95,7 +95,10 @@ int pcie_board_fix_fdt(void *fdt)
> >
> > svr = SVR_SOC_VER(get_svr());
> >
> >- if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 2, 0))
> >+ if ((svr == SVR_LX2160A || svr == SVR_LX2162A ||
> >+ svr == SVR_LX2120A || svr == SVR_LX2080A ||
> >+ svr == SVR_LX2122A || svr == SVR_LX2082A) &&
> >+ IS_SVR_REV(get_svr(), 2, 0))
> > return lx2_board_fix_fdt(fdt);
> >
> > return 0;
> >--
> >2.7.4
>
> egards
> Priyanka
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