[PATCH v2 08/30] clk: ti: add divider clock driver

Dario Binacchi dariobin at libero.it
Sun Sep 6 14:11:38 CEST 2020


The patch adds support for TI divider clock binding. The driver uses
routines provided by the common clock framework (ccf).

The code is based on the drivers/clk/ti/divider.c driver of the Linux
kernel.

Signed-off-by: Dario Binacchi <dariobin at libero.it>

---

Changes in v2:
- Merged to patch [09/31] clk: ti: refactor mux and divider clock
  drivers.

 .../clock/ti,autoidle.txt                     |  39 ++
 doc/device-tree-bindings/clock/ti,divider.txt | 117 ++++++
 drivers/clk/Kconfig                           |   6 +
 drivers/clk/Makefile                          |   2 +
 drivers/clk/clk-ti-divider.c                  | 380 ++++++++++++++++++
 drivers/clk/clk-ti-mux.c                      |  27 +-
 drivers/clk/clk-ti.c                          |  34 ++
 drivers/clk/clk-ti.h                          |  13 +
 8 files changed, 593 insertions(+), 25 deletions(-)
 create mode 100644 doc/device-tree-bindings/clock/ti,autoidle.txt
 create mode 100644 doc/device-tree-bindings/clock/ti,divider.txt
 create mode 100644 drivers/clk/clk-ti-divider.c
 create mode 100644 drivers/clk/clk-ti.c
 create mode 100644 drivers/clk/clk-ti.h

diff --git a/doc/device-tree-bindings/clock/ti,autoidle.txt b/doc/device-tree-bindings/clock/ti,autoidle.txt
new file mode 100644
index 0000000000..6c5b77e18c
--- /dev/null
+++ b/doc/device-tree-bindings/clock/ti,autoidle.txt
@@ -0,0 +1,39 @@
+Binding for Texas Instruments autoidle clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a register mapped
+clock which can be put to idle automatically by hardware based on the usage
+and a configuration bit setting. Autoidle clock is never an individual
+clock, it is always a derivative of some basic clock like a gate, divider,
+or fixed-factor.
+
+[1] doc/device-tree-bindings/clock/clock-bindings.txt
+
+Required properties:
+- reg : offset for the register controlling the autoidle
+- ti,autoidle-shift : bit shift of the autoidle enable bit
+- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
+
+Examples:
+	dpll_core_m4_ck: dpll_core_m4_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&dpll_core_x2_ck>;
+		ti,max-div = <31>;
+		ti,autoidle-shift = <8>;
+		reg = <0x2d38>;
+		ti,index-starts-at-one;
+		ti,invert-autoidle-bit;
+	};
+
+	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+		#clock-cells = <0>;
+		compatible = "ti,fixed-factor-clock";
+		clocks = <&dpll_usb_ck>;
+		ti,clock-div = <1>;
+		ti,autoidle-shift = <8>;
+		reg = <0x01b4>;
+		ti,clock-mult = <1>;
+		ti,invert-autoidle-bit;
+	};
diff --git a/doc/device-tree-bindings/clock/ti,divider.txt b/doc/device-tree-bindings/clock/ti,divider.txt
new file mode 100644
index 0000000000..3d0570e915
--- /dev/null
+++ b/doc/device-tree-bindings/clock/ti,divider.txt
@@ -0,0 +1,117 @@
+Binding for TI divider clock
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1].  It assumes a
+register-mapped adjustable clock rate divider that does not gate and has
+only one input clock or parent.  By default the value programmed into
+the register is one less than the actual divisor value.  E.g:
+
+register value		actual divisor value
+0			1
+1			2
+2			3
+
+This assumption may be modified by the following optional properties:
+
+ti,index-starts-at-one - valid divisor values start at 1, not the default
+of 0.  E.g:
+register value		actual divisor value
+1			1
+2			2
+3			3
+
+ti,index-power-of-two - valid divisor values are powers of two.  E.g:
+register value		actual divisor value
+0			1
+1			2
+2			4
+
+Additionally an array of valid dividers may be supplied like so:
+
+	ti,dividers = <4>, <8>, <0>, <16>;
+
+Which will map the resulting values to a divisor table by their index:
+register value		actual divisor value
+0			4
+1			8
+2			<invalid divisor, skipped>
+3			16
+
+Any zero value in this array means the corresponding bit-value is invalid
+and must not be used.
+
+The binding must also provide the register to control the divider and
+unless the divider array is provided, min and max dividers. Optionally
+the number of bits to shift that mask, if necessary. If the shift value
+is missing it is the same as supplying a zero shift.
+
+This binding can also optionally provide support to the hardware autoidle
+feature, see [2].
+
+[1] doc/device-tree-bindings/clock/clock/clock-bindings.txt
+[2] doc/device-tree-bindings/clock/ti,autoidle.txt
+
+Required properties:
+- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable divider
+
+Optional properties:
+- clock-output-names : from common clock binding.
+- ti,dividers : array of integers defining divisors
+- ti,bit-shift : number of bits to shift the divider value, defaults to 0
+- ti,min-div : min divisor for dividing the input clock rate, only
+  needed if the first divisor is offset from the default value (1)
+- ti,max-div : max divisor for dividing the input clock rate, only needed
+  if ti,dividers is not defined.
+- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
+  only valid if ti,dividers is not defined.
+- ti,index-power-of-two : valid divisor programming must be a power of two,
+  only valid if ti,dividers is not defined.
+- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
+  see [2]
+- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
+  see [2]
+- ti,set-rate-parent : clk_set_rate is propagated to parent
+- ti,latch-bit : latch the divider value to HW, only needed if the register
+  access requires this. As an example dra76x DPLL_GMAC H14 divider implements
+  such behavior.
+
+Examples:
+dpll_usb_m2_ck: dpll_usb_m2_ck at 4a008190 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&dpll_usb_ck>;
+	ti,max-div = <127>;
+	reg = <0x190>;
+	ti,index-starts-at-one;
+};
+
+aess_fclk: aess_fclk at 4a004528 {
+	#clock-cells = <0>;
+	compatible = "ti,divider-clock";
+	clocks = <&abe_clk>;
+	ti,bit-shift = <24>;
+	reg = <0x528>;
+	ti,max-div = <2>;
+};
+
+dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+	#clock-cells = <0>;
+	compatible = "ti,composite-divider-clock";
+	clocks = <&dpll_core_x2_ck>;
+	ti,max-div = <31>;
+	reg = <0x0134>;
+	ti,index-starts-at-one;
+};
+
+ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+	#clock-cells = <0>;
+	compatible = "ti,composite-divider-clock";
+	clocks = <&corex2_fck>;
+	ti,bit-shift = <8>;
+	reg = <0x0a40>;
+	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+};
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index bddb454b7c..d7b546d9db 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -105,6 +105,12 @@ config CLK_TI_AM3_DPLL
 	  This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
 	  provides all interface clocks and functional clocks to the processor.
 
+config CLK_TI_DIVIDER
+	bool "TI divider clock driver"
+	depends on CLK && OF_CONTROL && CLK_CCF
+	help
+	  This enables the divider clock driver support on TI's SoCs.
+
 config CLK_TI_MUX
 	bool "TI mux clock driver"
 	depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index cc20279a20..21b1e9c364 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
 obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
 obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
 obj-$(CONFIG_ARCH_MESON) += meson/
+obj-$(CONFIG_ARCH_OMAP2PLUS) += clk-ti.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_ARCH_SOCFPGA) += altera/
 obj-$(CONFIG_CLK_AT91) += at91/
@@ -47,6 +48,7 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
 obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
 obj-$(CONFIG_STM32H7) += clk_stm32h7.o
 obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-ti-am3-dpll.o clk-ti-am3-dpll-x2.o
+obj-$(CONFIG_CLK_TI_DIVIDER) += clk-ti-divider.o
 obj-$(CONFIG_CLK_TI_MUX) += clk-ti-mux.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
 obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
diff --git a/drivers/clk/clk-ti-divider.c b/drivers/clk/clk-ti-divider.c
new file mode 100644
index 0000000000..e89650883b
--- /dev/null
+++ b/drivers/clk/clk-ti-divider.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI divider clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin at libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/divider.c
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include "clk-ti.h"
+
+/*
+ * The reverse of DIV_ROUND_UP: The maximum number which
+ * divided by m is r
+ */
+#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
+
+struct clk_ti_divider_priv {
+	struct clk parent;
+	fdt_addr_t reg;
+	const struct clk_div_table *table;
+	u8 shift;
+	u8 flags;
+	u8 div_flags;
+	s8 latch;
+	u16 min;
+	u16 max;
+	u16 mask;
+};
+
+static unsigned int _get_div(const struct clk_div_table *table, ulong flags,
+			     unsigned int val)
+{
+	if (flags & CLK_DIVIDER_ONE_BASED)
+		return val;
+
+	if (flags & CLK_DIVIDER_POWER_OF_TWO)
+		return 1 << val;
+
+	if (table)
+		return clk_divider_get_table_div(table, val);
+
+	return val + 1;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table, ulong flags,
+			     unsigned int div)
+{
+	if (flags & CLK_DIVIDER_ONE_BASED)
+		return div;
+
+	if (flags & CLK_DIVIDER_POWER_OF_TWO)
+		return __ffs(div);
+
+	if (table)
+		return clk_divider_get_table_val(table, div);
+
+	return div - 1;
+}
+
+static int _div_round_up(const struct clk_div_table *table, ulong parent_rate,
+			 ulong rate)
+{
+	const struct clk_div_table *clkt;
+	int up = INT_MAX;
+	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+	for (clkt = table; clkt->div; clkt++) {
+		if (clkt->div == div)
+			return clkt->div;
+		else if (clkt->div < div)
+			continue;
+
+		if ((clkt->div - div) < (up - div))
+			up = clkt->div;
+	}
+
+	return up;
+}
+
+static int _div_round(const struct clk_div_table *table, ulong parent_rate,
+		      ulong rate)
+{
+	if (table)
+		return _div_round_up(table, parent_rate, rate);
+
+	return DIV_ROUND_UP(parent_rate, rate);
+}
+
+static int clk_ti_divider_best_div(struct clk *clk, ulong rate,
+				   ulong *best_parent_rate)
+{
+	struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+	ulong parent_rate, parent_round_rate, max_div;
+	ulong best_rate, r;
+	int i, best_div = 0;
+
+	parent_rate = clk_get_rate(&priv->parent);
+	if (IS_ERR_VALUE(parent_rate))
+		return parent_rate;
+
+	if (!rate)
+		rate = 1;
+
+	if (!(clk->flags & CLK_SET_RATE_PARENT)) {
+		best_div = _div_round(priv->table, parent_rate, rate);
+		if (best_div == 0)
+			best_div = 1;
+
+		if (best_div > priv->max)
+			best_div = priv->max;
+
+		*best_parent_rate = parent_rate;
+		return best_div;
+	}
+
+	max_div = min(ULONG_MAX / rate, (ulong)priv->max);
+	for (best_rate = 0, i = 1; i <= max_div; i++) {
+		if (!clk_divider_is_valid_div(priv->table, priv->div_flags, i))
+			continue;
+
+		/*
+		 * It's the most ideal case if the requested rate can be
+		 * divided from parent clock without needing to change
+		 * parent rate, so return the divider immediately.
+		 */
+		if ((rate * i) == parent_rate) {
+			*best_parent_rate = parent_rate;
+			dev_dbg(dev, "rate=%ld, best_rate=%ld, div=%d\n", rate,
+				rate, i);
+			return i;
+		}
+
+		parent_round_rate = clk_round_rate(&priv->parent,
+						   MULT_ROUND_UP(rate, i));
+		if (IS_ERR_VALUE(parent_round_rate))
+			continue;
+
+		r = DIV_ROUND_UP(parent_round_rate, i);
+		if (r <= rate && r > best_rate) {
+			best_div = i;
+			best_rate = r;
+			*best_parent_rate = parent_round_rate;
+			if (best_rate == rate)
+				break;
+		}
+	}
+
+	if (best_div == 0) {
+		best_div = priv->max;
+		parent_round_rate = clk_round_rate(&priv->parent, 1);
+		if (IS_ERR_VALUE(parent_round_rate))
+			return parent_round_rate;
+	}
+
+	dev_dbg(dev, "rate=%ld, best_rate=%ld, div=%d\n", rate, best_rate,
+		best_div);
+
+	return best_div;
+}
+
+static ulong clk_ti_divider_round_rate(struct clk *clk, ulong rate)
+{
+	ulong parent_rate;
+	int div;
+
+	div = clk_ti_divider_best_div(clk, rate, &parent_rate);
+	if (div < 0)
+		return div;
+
+	return DIV_ROUND_UP(parent_rate, div);
+}
+
+static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+	ulong parent_rate;
+	int div;
+	u32 val, v;
+
+	div = clk_ti_divider_best_div(clk, rate, &parent_rate);
+	if (div < 0)
+		return div;
+
+	if (clk->flags & CLK_SET_RATE_PARENT) {
+		parent_rate = clk_set_rate(&priv->parent, parent_rate);
+		if (IS_ERR_VALUE(parent_rate))
+			return parent_rate;
+	}
+
+	val = _get_val(priv->table, priv->div_flags, div);
+
+	v = readl(priv->reg);
+	v &= ~(priv->mask << priv->shift);
+	v |= val << priv->shift;
+	writel(v, priv->reg);
+	clk_ti_latch(priv->reg, priv->latch);
+
+	return clk_get_rate(clk);
+}
+
+static ulong clk_ti_divider_get_rate(struct clk *clk)
+{
+	struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+	ulong rate, parent_rate;
+	unsigned int div;
+	u32 v;
+
+	parent_rate = clk_get_rate(&priv->parent);
+	if (IS_ERR_VALUE(parent_rate))
+		return parent_rate;
+
+	v = readl(priv->reg) >> priv->shift;
+	v &= priv->mask;
+
+	div = _get_div(priv->table, priv->div_flags, v);
+	if (!div) {
+		if (!(priv->div_flags & CLK_DIVIDER_ALLOW_ZERO))
+			dev_warn(clk->dev,
+				 "zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n");
+		return parent_rate;
+	}
+
+	rate = DIV_ROUND_UP(parent_rate, div);
+	dev_dbg(clk->dev, "rate=%ld\n", rate);
+	return rate;
+}
+
+static int clk_ti_divider_request(struct clk *clk)
+{
+	struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+
+	clk->flags = priv->flags;
+	return 0;
+}
+
+const struct clk_ops clk_ti_divider_ops = {
+	.request = clk_ti_divider_request,
+	.round_rate = clk_ti_divider_round_rate,
+	.get_rate = clk_ti_divider_get_rate,
+	.set_rate = clk_ti_divider_set_rate
+};
+
+static int clk_ti_divider_remove(struct udevice *dev)
+{
+	struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+	int err;
+
+	err = clk_release_all(&priv->parent, 1);
+	if (err) {
+		dev_err(dev, "failed to release parent clock\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int clk_ti_divider_probe(struct udevice *dev)
+{
+	struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+	int err;
+
+	err = clk_get_by_index(dev, 0, &priv->parent);
+	if (err) {
+		dev_err(dev, "failed to get parent clock\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static int clk_ti_divider_ofdata_to_platdata(struct udevice *dev)
+{
+	struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+	struct clk_div_table *table = NULL;
+	u32 val, valid_div;
+	u32 min_div = 0;
+	u32 max_val, max_div = 0;
+	u16 mask;
+	int i, div_num;
+
+	priv->reg = dev_read_addr(dev);
+	dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+	priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
+	priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
+	if (dev_read_bool(dev, "ti,index-starts-at-one"))
+		priv->div_flags |= CLK_DIVIDER_ONE_BASED;
+
+	if (dev_read_bool(dev, "ti,index-power-of-two"))
+		priv->div_flags |= CLK_DIVIDER_POWER_OF_TWO;
+
+	if (dev_read_bool(dev, "ti,set-rate-parent"))
+		priv->flags |= CLK_SET_RATE_PARENT;
+
+	if (dev_read_prop(dev, "ti,dividers", &div_num)) {
+		div_num /= sizeof(u32);
+
+		/* Determine required size for divider table */
+		for (i = 0, valid_div = 0; i < div_num; i++) {
+			dev_read_u32_index(dev, "ti,dividers", i, &val);
+			if (val)
+				valid_div++;
+		}
+
+		if (!valid_div) {
+			dev_err(dev, "no valid dividers\n");
+			return -EINVAL;
+		}
+
+		table = calloc(valid_div + 1, sizeof(*table));
+		if (!table)
+			return -ENOMEM;
+
+		for (i = 0, valid_div = 0; i < div_num; i++) {
+			dev_read_u32_index(dev, "ti,dividers", i, &val);
+			if (!val)
+				continue;
+
+			table[valid_div].div = val;
+			table[valid_div].val = i;
+			valid_div++;
+			if (val > max_div)
+				max_div = val;
+
+			if (!min_div || val < min_div)
+				min_div = val;
+		}
+
+		max_val = max_div;
+	} else {
+		/* Divider table not provided, determine min/max divs */
+		min_div = dev_read_u32_default(dev, "ti,min-div", 1);
+		if (dev_read_u32(dev, "ti,max-div", &max_div)) {
+			dev_err(dev, "missing 'max-div' property\n");
+			return -EFAULT;
+		}
+
+		max_val = max_div;
+		if (!(priv->div_flags & CLK_DIVIDER_ONE_BASED) &&
+		    !(priv->div_flags & CLK_DIVIDER_POWER_OF_TWO))
+			max_val--;
+	}
+
+	priv->table = table;
+	priv->min = min_div;
+	priv->max = max_div;
+
+	if (priv->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+		mask = fls(max_val) - 1;
+	else
+		mask = max_val;
+
+	priv->mask = (1 << fls(mask)) - 1;
+	return 0;
+}
+
+static const struct udevice_id clk_ti_divider_of_match[] = {
+	{.compatible = "ti,divider-clock"},
+	{}
+};
+
+U_BOOT_DRIVER(clk_ti_divider) = {
+	.name = "ti_divider_clock",
+	.id = UCLASS_CLK,
+	.of_match = clk_ti_divider_of_match,
+	.ofdata_to_platdata = clk_ti_divider_ofdata_to_platdata,
+	.probe = clk_ti_divider_probe,
+	.remove = clk_ti_divider_remove,
+	.priv_auto_alloc_size = sizeof(struct clk_ti_divider_priv),
+	.ops = &clk_ti_divider_ops,
+};
diff --git a/drivers/clk/clk-ti-mux.c b/drivers/clk/clk-ti-mux.c
index 7e39dd3477..e4b190bbcc 100644
--- a/drivers/clk/clk-ti-mux.c
+++ b/drivers/clk/clk-ti-mux.c
@@ -12,6 +12,7 @@
 #include <clk-uclass.h>
 #include <asm/io.h>
 #include <linux/clk-provider.h>
+#include "clk-ti.h"
 
 struct clk_ti_mux_priv {
 	struct clk_bulk parents;
@@ -23,30 +24,6 @@ struct clk_ti_mux_priv {
 	s32 latch;
 };
 
-static void clk_ti_mux_rmw(u32 val, u32 mask, fdt_addr_t reg)
-{
-	u32 v;
-
-	v = readl(reg);
-	v &= ~mask;
-	v |= val;
-	writel(v, reg);
-}
-
-static void clk_ti_mux_latch(fdt_addr_t reg, s8 shift)
-{
-	u32 latch;
-
-	if (shift < 0)
-		return;
-
-	latch = 1 << shift;
-
-	clk_ti_mux_rmw(latch, latch, reg);
-	clk_ti_mux_rmw(0, latch, reg);
-	readl(reg);		/* OCP barrier */
-}
-
 static struct clk *clk_ti_mux_get_parent_by_index(struct clk_bulk *parents,
 						  int index)
 {
@@ -119,7 +96,7 @@ static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)
 
 	val |= index << priv->shift;
 	writel(val, priv->reg);
-	clk_ti_mux_latch(priv->reg, priv->latch);
+	clk_ti_latch(priv->reg, priv->latch);
 	return 0;
 }
 
diff --git a/drivers/clk/clk-ti.c b/drivers/clk/clk-ti.c
new file mode 100644
index 0000000000..594ef75270
--- /dev/null
+++ b/drivers/clk/clk-ti.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI clock utilities
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin at libero.it>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "clk-ti.h"
+
+static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
+{
+	u32 v;
+
+	v = readl(reg);
+	v &= ~mask;
+	v |= val;
+	writel(v, reg);
+}
+
+void clk_ti_latch(fdt_addr_t reg, s8 shift)
+{
+	u32 latch;
+
+	if (shift < 0)
+		return;
+
+	latch = 1 << shift;
+
+	clk_ti_rmw(latch, latch, reg);
+	clk_ti_rmw(0, latch, reg);
+	readl(reg);		/* OCP barrier */
+}
diff --git a/drivers/clk/clk-ti.h b/drivers/clk/clk-ti.h
new file mode 100644
index 0000000000..601c3823f7
--- /dev/null
+++ b/drivers/clk/clk-ti.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * TI clock utilities header
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin at libero.it>
+ */
+
+#ifndef _CLK_TI_H
+#define _CLK_TI_H
+
+void clk_ti_latch(fdt_addr_t reg, s8 shift);
+
+#endif /* #ifndef _CLK_TI_H */
-- 
2.17.1



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