[PATCH v7 05/21] arm: mvebu: x530: Use tiny SPI NOR

Chris Packham Chris.Packham at alliedtelesis.co.nz
Mon Sep 7 01:23:45 CEST 2020


On 7/09/20 11:07 am, Chris Packham wrote:
> Hi Pratyush,
>
> On 5/09/20 3:39 am, Pratyush Yadav wrote:
>> Chris,
>>
>> On 04/09/20 09:04PM, Pratyush Yadav wrote:
>>> The SPI NOR core will get Octal DTR in following commits. This has
>>> presented a significant challenge of keeping the SPL size in check on
>>> the x530 platform.
>>>
>>> On a previous iteration of the series, adding a set of compile-time
>>> switches got the build working. But rebasing on the latest master 
>>> breaks
>>> the build again. We are fighting a losing battle here. Every 
>>> addition to
>>> either the SPI NOR core in the future, or any other core part of U-Boot
>>> will potentially lead to the SPL size going beyond the limit and the
>>> build failing.
>>>
>>> To combat this we will have to keep adding more and more compile-time
>>> switches, increasing the complexity of the code in the process. This is
>>> not sustainable. So use tiny SPI NOR instead. It is designed with
>>> size-limited SPL binaries in mind, and will afford us more breathing
>>> room.
>>>
>>> To enable tiny SPI NOR, CONFIG_SPI_FLASH_BAR has to be disabled.
>>>
>>> Signed-off-by: Pratyush Yadav <p.yadav at ti.com>
>>> ---
>>>   configs/x530_defconfig | 1 -
>>>   1 file changed, 1 deletion(-)
>> Can you please test these changes on your board and confirm that tiny
>> SPI NOR works for you?
>
> It booted OK but when I try to write something to SPI flash I get an 
> error
>
> => sf probe
> SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, 
> total 16 MiB
> => sf update ${fileaddr} 0 ${filesize} device 0 offset 0x0, size 0x100000
> SPI flash failed in erase step
>
> => sf erase 0 0x100000
> SF: 1048576 bytes @ 0x0 Erased: ERROR
>
> Unfortunately I didn't test this before applying your series so I'm 
> not sure if it is because of your changes or a preexisting issue with 
> v2020.10-rc3
>
Booting with v2020.10-rc3-00086-ge5df264e7aac (i.e. master as of this 
morning) I can write to SPI flash so it looks like it is something in 
your series. Let me know if you want me to try something else out.
>>> diff --git a/configs/x530_defconfig b/configs/x530_defconfig
>>> index 890c94b5c1..0570dbe9ea 100644
>>> --- a/configs/x530_defconfig
>>> +++ b/configs/x530_defconfig
>>> @@ -62,7 +62,6 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y
>>>   CONFIG_NAND_PXA3XX=y
>>>   CONFIG_SF_DEFAULT_BUS=1
>>>   CONFIG_SF_DEFAULT_SPEED=50000000
>>> -CONFIG_SPI_FLASH_BAR=y
>>>   CONFIG_SPI_FLASH_MACRONIX=y
>>>   CONFIG_SPI_FLASH_STMICRO=y
>>>   CONFIG_SPI_FLASH_SST=y


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