[PATCH] ARM: dts: stm32: Adjust PLL4 settings on AV96 again

[Patrick DELAUNAY]

Hi Marek,

> From: Marek Vasut <marex at denx.de>
> Sent: samedi 22 août 2020 22:45
> 
> PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
> 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate
> clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The
> PLL4P/PLL4R are generating 99 MHz instead of 100 MHz, which is in tolerance for
> the SDMMC.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Gerald Baeza <gerald.baeza at st.com>
> Cc: Patrick Delaunay <patrick.delaunay at st.com>
> Cc: Patrice Chotard <patrice.chotard at st.com>
> ---
> NOTE: Thanks to Gerald for this suggestion.
> ---
>  arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> index 7529068c51..c73318488d 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
> @@ -132,11 +132,11 @@
>  		u-boot,dm-pre-reloc;
>  	};
> 
> -	/* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
> +	/* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
>  	pll4: st,pll at 3 {
>  		compatible = "st,stm32mp1-pll";
>  		reg = <3>;
> -		cfg = < 1 49 5 11 5 PQR(1,1,1) >;
> +		cfg = < 3 98 5 7 5 PQR(1,1,1) >;
>  		u-boot,dm-pre-reloc;
>  	};
>  };
> --
> 2.28.0

Reviewed-by: Patrick Delaunay <patrick.delaunay at st.com>

Applied to u-boot-stm/master, thanks!

Thanks

Patrick