[PATCH 7/7] riscv: Add some comments to start.S

[Bin Meng]

On Tue, Sep 8, 2020 at 2:17 AM Sean Anderson <seanga2 at gmail.com> wrote:
>
> This adds comments regarding the ordering and purpose of certain
> instructions as I understand them.
>
> Signed-off-by: Sean Anderson <seanga2 at gmail.com>
> ---
>
>  arch/riscv/cpu/start.S | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> index 59d3d7bbf4..c659c6df53 100644
> --- a/arch/riscv/cpu/start.S
> +++ b/arch/riscv/cpu/start.S
> @@ -43,7 +43,10 @@ _start:
>         csrr    a0, CSR_MHARTID
>  #endif
>
> -       /* save hart id and dtb pointer */
> +       /*
> +        * Save hart id and dtb pointer. The thread pointer register is not

U-Boot does not use tp register in C code.

> +        * modified by C code, and may be used in trap handlers.
> +        */
>         mv      tp, a0
>         mv      s1, a1
>
> @@ -54,10 +57,18 @@ _start:
>          */
>         mv      gp, zero
>
> +       /*
> +        * Set the trap handler. This must happen after initializing tp and gp
> +        * because the handler may use these registers.
> +        */
>         la      t0, trap_entry
>         csrw    MODE_PREFIX(tvec), t0
>
> -       /* mask all interrupts */
> +       /*
> +        * Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
> +        * for U-Boot, but we will need to read m/sip to determine if we get an
> +        * IPI
> +        */
>         csrw    MODE_PREFIX(ie), zero
>
>  #if CONFIG_IS_ENABLED(SMP)
> @@ -407,6 +418,10 @@ secondary_hart_relocate:
>         mv      gp, a2
>  #endif
>
> +/*
> + * Interrupts are disabled globally, but they can still be read from m/sip. The
> + * wfi function will wake us up if we get an IPI, even if we do not trap.
> + */
>  secondary_hart_loop:
>         wfi

Regards,
Bin