[PATCH v7 1/2] board: kontron: add sl28 support
Heiko Thiery
heiko.thiery at gmail.com
Mon Sep 14 13:01:54 CEST 2020
Hi Michael,
Am Mo., 7. Sept. 2020 um 23:08 Uhr schrieb Michael Walle <michael at walle.cc>:
>
> Add basic support for the Kontron SMARC-sAL28 board. This includes just
> the bare minimum to be able to bring up the board and boot linux.
>
> For now, the Single and Dual PHY variant is supported. Other variants
> will fall back to the basic variant.
>
> In particular, there is no watchdog support for now. This means that you
> have to disable the default watchdog, otherwise you'll end up in the
> recovery bootloader. See the board README for details.
>
> Signed-off-by: Michael Walle <michael at walle.cc>
After applying the patch
(https://patchwork.ozlabs.org/project/uboot/patch/20200803221633.24096-1-michael@walle.cc/)
I could boot the mainline kernel.
Tested-by: Heiko Thiery <heiko.thiery at gmail.com>
> ---
> arch/arm/Kconfig | 11 +
> arch/arm/dts/Makefile | 3 +
> .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 135 +++++++++++++
> .../fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi | 2 +
> .../arm/dts/fsl-ls1028a-kontron-sl28-var3.dts | 15 ++
> .../fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi | 2 +
> .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 48 +++++
> arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 189 ++++++++++++++++++
> board/kontron/sl28/Kconfig | 18 ++
> board/kontron/sl28/MAINTAINERS | 7 +
> board/kontron/sl28/Makefile | 8 +
> board/kontron/sl28/common.c | 10 +
> board/kontron/sl28/ddr.c | 98 +++++++++
> board/kontron/sl28/sl28.c | 68 +++++++
> board/kontron/sl28/spl.c | 32 +++
> configs/kontron_sl28_defconfig | 107 ++++++++++
> doc/board/index.rst | 1 +
> doc/board/kontron/index.rst | 9 +
> doc/board/kontron/sl28.rst | 160 +++++++++++++++
> include/configs/kontron_sl28.h | 108 ++++++++++
> 20 files changed, 1031 insertions(+)
> create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
> create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
> create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dts
> create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
> create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
> create mode 100644 arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
> create mode 100644 board/kontron/sl28/Kconfig
> create mode 100644 board/kontron/sl28/MAINTAINERS
> create mode 100644 board/kontron/sl28/Makefile
> create mode 100644 board/kontron/sl28/common.c
> create mode 100644 board/kontron/sl28/ddr.c
> create mode 100644 board/kontron/sl28/sl28.c
> create mode 100644 board/kontron/sl28/spl.c
> create mode 100644 configs/kontron_sl28_defconfig
> create mode 100644 doc/board/kontron/index.rst
> create mode 100644 doc/board/kontron/sl28.rst
> create mode 100644 include/configs/kontron_sl28.h
>
[snip]
> --- a/doc/board/index.rst
> +++ b/doc/board/index.rst
> @@ -15,6 +15,7 @@ Board-specific doc
> freescale/index
> google/index
> intel/index
> + kontron/index
> renesas/index
> rockchip/index
> sifive/index
> diff --git a/doc/board/kontron/index.rst b/doc/board/kontron/index.rst
> new file mode 100644
> index 0000000000..543b22e2f5
> --- /dev/null
> +++ b/doc/board/kontron/index.rst
> @@ -0,0 +1,9 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Kontron
> +=======
> +
> +.. toctree::
> + :maxdepth: 2
> +
> + sl28
> diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst
> new file mode 100644
> index 0000000000..e458fbc607
> --- /dev/null
> +++ b/doc/board/kontron/sl28.rst
> @@ -0,0 +1,160 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Summary
> +=======
> +
> +The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
> +processor module with an on-chip 6-port TSN switch and a 3D GPU.
> +
> +
> +Quickstart
> +==========
> +
> +Compile U-Boot
> +--------------
> +
> +Configure and compile the binary::
> +
> + $ make kontron_sl28_defconfig
> + $ CROSS_COMPILE=aarch64-linux-gnu make
Small typo here. A missing '-'.
$ CROSS_COMPILE=aarch64-linux-gnu- make
> +
> +Copy u-boot.rom to a TFTP server.
> +
> +Install the bootloader on the board
> +-----------------------------------
> +
> +Please note, this bootloader doesn't support the builtin watchdog (yet),
> +therefore you have to disable it, see below. Otherwise you'll end up in
> +the failsafe bootloader on every reset::
> +
> + > tftp path/to/u-boot.rom
> + > sf probe 0
> + > sf update $fileaddr 0x210000 $filesize
> +
> +The board is fully failsafe, you can't break anything. But because you've
> +disabled the builtin watchdog you might have to manually enter failsafe
> +mode by asserting the ``FORCE_RECOV#`` line during board reset.
> +
> +Disable the builtin watchdog
> +----------------------------
> +
> +- boot into the failsafe bootloader, either by asserting the
> + ``FORCE_RECOV#`` line or if you still have the original bootloader
> + installed you can use the command::
> +
> + > wdt dev cpld_watchdog at 4a; wdt expire 1
> +
> +- in the failsafe bootloader use the "sl28 nvm" command to disable
> + the automatic start of the builtin watchdog::
> +
> + > sl28 nvm 0008
> +
> +- power-cycle the board
> +
> +
> +Useful I2C tricks
> +=================
> +
> +The board has a board management controller which is not supported in
> +u-boot (yet). But you can use the i2c command to access it.
> +
> +- reset into failsafe bootloader::
> +
> + > i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
> +
> +- read board management controller version::
> +
> + > i2c md 4a 3.1 1
> +
> +
> +Non-volatile Board Configuration Bits
> +=====================================
> +
> +The board has 16 configuration bits which are stored in the CPLD and are
> +non-volatile. These can be changed by the `sl28 nvm` command.
> +
> +=== ===============================================================
> +Bit Description
> +=== ===============================================================
> + 0 Power-on inhibit
> + 1 Enable eMMC boot
> + 2 Enable watchdog by default
> + 3 Disable failsafe watchdog by default
> + 4 Clock generator selection bit 0
> + 5 Clock generator selection bit 1
> + 6 Disable CPU SerDes clock #2 and PCIe-A clock output
> + 7 Disable PCIe-B and PCIe-C clock output
> + 8 Keep onboard PHYs in reset
> + 9 Keep USB hub in reset
> + 10 Keep eDP-to-LVDS converter in reset
> + 11 Enable I2C stuck recovery on I2C PM and I2C GP busses
> + 12 Enable automatic onboard PHY H/W reset
> + 13 reserved
> + 14 Used by the RCW to determine boot source
> + 15 Used by the RCW to determine boot source
> +=== ===============================================================
> +
> +Please note, that if the board is in failsafe mode, the bits will have the
> +factory defaults, ie. all bits are off.
> +
> +Power-On Inhibit
> +----------------
> +
> +If this is set, the board doesn't automatically turn on when power is
> +applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
> +use any other wake-up source such as RTC alarm or Wake-on-LAN.
> +
> +eMMC Boot
> +---------
> +
> +If this is set, the RCW will be fetched from the on-board eMMC at offset
> +1MiB. For further details, have a look at the `Reset Configuration Word
> +Documentation`_.
> +
> +Watchdog
> +--------
> +
> +By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
> +3, the user can change its mode or disable it altogether.
> +
> +===== ===== ===============================
> +Bit 2 Bit 3 Description
> +===== ===== ===============================
> + 0 0 Watchdog enabled, failsafe mode
> + 0 1 Watchdog disabled
> + 1 0 Watchdog enabled, failsafe mode
> + 1 1 Watchdog enabled, normal mode
> +===== ===== ===============================
> +
> +Clock Generator Select
> +----------------------
> +
> +The board is prepared to supply different SerDes clock speeds. But for now,
> +only setting 0 is supported, otherwise the CPU will hang because the PLL
> +will not lock.
> +
> +Clock Output Disable And Keep Devices In Reset
> +----------------------------------------------
> +
> +To safe power, the user might disable different devices and clock output of
> +the board. It is not supported to disable the "CPU SerDes clock #2" for
> +now, otherwise the CPU will hang because the PLL will not lock.
> +
> +Automatic reset of the onboard PHYs
> +-----------------------------------
> +
> +By default, there is no hardware reset of the onboard PHY. This is because
> +for Wake-on-LAN, some registers have to retain their values. If you don't
> +use the WOL feature and a soft reset of the PHY is not enough you can
> +enable the hardware reset. The onboard PHY hardware reset follows the
> +power-on reset.
> +
> +
> +Further documentation
> +=====================
> +
> +- `Vendor Documentation`_
> +- `Reset Configuration Word Documentation`_
> +
> +.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md
> +.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md
> diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
> new file mode 100644
> index 0000000000..afe512a8c7
> --- /dev/null
> +++ b/include/configs/kontron_sl28.h
> @@ -0,0 +1,108 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +
> +#ifndef __SL28_H
> +#define __SL28_H
> +
> +#include <asm/arch/stream_id_lsch3.h>
> +#include <asm/arch/config.h>
> +#include <asm/arch/soc.h>
> +
> +/* we don't use hwconfig but this has to be defined.. */
> +#define HWCONFIG_BUFFER_SIZE 256
> +
> +/* we don't have secure memory unless we have a BL31 */
> +#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
> +#undef CONFIG_SYS_MEM_RESERVE_SECURE
> +#endif
> +
> +/* DDR */
> +#define CONFIG_DDR_ECC
> +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
> +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
> +
> +#define CONFIG_VERY_BIG_RAM
> +#define CONFIG_CHIP_SELECTS_PER_CTRL 4
> +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
> +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
> +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
> +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
> +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
> +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
> +
> +/* early stack pointer */
> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xeff0)
> +
> +/* memtest command */
> +#define CONFIG_SYS_MEMTEST_START 0x80000000
> +#define CONFIG_SYS_MEMTEST_END 0x9fffffff
> +
> +/* SMP */
> +#define CPU_RELEASE_ADDR secondary_boot_addr
> +
> +/* generic timer */
> +#define COUNTER_FREQUENCY 25000000
> +
> +/* size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
> +
> +/* early heap for SPL DM */
> +#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE
> +
> +/* serial port */
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE 1
> +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +#define CONFIG_SYS_CLK_FREQ 100000000
> +#define CONFIG_DDR_CLK_FREQ 100000000
> +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
> +
> +/* MMC */
> +#ifdef CONFIG_MMC
> +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
> +#endif
> +
> +/* ethernet */
> +#define CONFIG_SYS_RX_ETH_BUFFER 8
> +
> +/* SPL */
> +#define CONFIG_SPL_BSS_START_ADDR 0x80100000
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
> +#define CONFIG_SPL_MAX_SIZE 0x20000
> +#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
> +
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
> +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
> +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
> +
> +/* environment */
> +/* see include/configs/ti_armv7_common.h */
> +#define CONFIG_SYS_LOAD_ADDR 0x82000000
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "loadaddr=0x82000000\0" \
> + "kernel_addr_r=0x82000000\0" \
> + "fdt_addr_r=0x88000000\0" \
> + "bootm_size=0x10000000\0" \
> + "pxefile_addr_r=0x80100000\0" \
> + "scriptaddr=0x80000000\0" \
> + "ramdisk_addr_r=0x88080000\0"
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + func(MMC, mmc, 1) \
> + func(MMC, mmc, 0) \
> + func(NVME, nvme, 0) \
> + func(USB, usb, 0) \
> + func(DHCP, dhcp, 0) \
> + func(PXE, pxe, 0)
> +#include <config_distro_bootcmd.h>
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "env_addr=0x203e0004\0" \
> + "envload=env import -d -b ${env_addr}\0" \
> + "install_rcw=source 20200000\0" \
> + "fdtfile=freescale/fsl-ls1028a-kontron-sl28.dtb\0" \
> + ENV_MEM_LAYOUT_SETTINGS \
> + BOOTENV
> +
> +#endif /* __SL28_H */
> --
> 2.20.1
>
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