[PATCH 3/5] imx8mq: fix SSCG_PLL_REFCLK_SEL_x

[peng.fan at nxp.com]

From: Peng Fan <peng.fan at nxp.com>

Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16

Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan at nxp.com>
Reviewed-by: Ye Li <ye.li at nxp.com>
---
 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
index 7109d334fa..340a61e55b 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -358,10 +358,10 @@ enum clk_src_index {
 #define SSCG_PLL_LOCK_SEL_MASK		BIT(3)
 #define SSCG_PLL_COUNTCLK_SEL_MASK	BIT(2)
 #define SSCG_PLL_REFCLK_SEL_MASK	0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M	BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M	(1)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3)
 
 #define SSCG_PLL_SSDS_MASK		BIT(8)
 #define SSCG_PLL_SSMD_MASK		(0x7 << 5)
-- 
2.28.0