[PATCH v3 1/7] Revert "riscv: Clear pending interrupts before enabling IPIs"
Sean Anderson
seanga2 at gmail.com
Mon Sep 21 13:51:35 CEST 2020
Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.
The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.
This reverts commit 9472630337e7c4ac442066b5a752aaa8c3b4d4a6.
Signed-off-by: Sean Anderson <seanga2 at gmail.com>
Reviewed-by: Bin Meng <bin.meng at windriver.com>
---
(no changes since v1)
arch/riscv/cpu/start.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bf9fdf369b..e3222b1ea7 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -65,8 +65,6 @@ _start:
#else
li t0, SIE_SSIE
#endif
- /* Clear any pending IPIs */
- csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0
#endif
--
2.28.0
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