[PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices

[Wolfgang Wallner]

Hi Simon,

-----"Simon Glass" <sjg at chromium.org> schrieb: -----
> Betreff: Re: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices
> 
> Hi Wolfgang,
> 
> On Mon, 21 Sep 2020 at 07:50, Wolfgang Wallner
> <wolfgang.wallner at br-automation.com> wrote:
> >
> > Hi Simon,
> >
> > -----"Simon Glass" <sjg at chromium.org> schrieb: -----
> > > Betreff: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices
> > >
> > > Add common x86 ASL files, taken from coreboot.
> > >
> > > Signed-off-by: Simon Glass <sjg at chromium.org>
> > > ---
> > >
> > > (no changes since v1)
> > >
> > >  arch/x86/include/asm/acpi/chromeos.asl    | 108 +++++++++++++++++
> > >  arch/x86/include/asm/acpi/cpu.asl         |  25 ++++
> > >  arch/x86/include/asm/acpi/cros_gnvs.asl   |  29 +++++
> > >  arch/x86/include/asm/acpi/lpc.asl         | 141 ++++++++++++++++++++++
> > >  arch/x86/include/asm/acpi/pci_osc.asl     |  21 ++++
> > >  arch/x86/include/asm/acpi/pcr.asl         |  80 ++++++++++++
> > >  arch/x86/include/asm/acpi/ramoops.asl     |  32 +++++
> > >  arch/x86/include/asm/acpi/sleepstates.asl |  12 +-
> > >  8 files changed, 443 insertions(+), 5 deletions(-)
> > >  create mode 100644 arch/x86/include/asm/acpi/chromeos.asl
> > >  create mode 100644 arch/x86/include/asm/acpi/cpu.asl
> > >  create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl
> > >  create mode 100644 arch/x86/include/asm/acpi/lpc.asl
> > >  create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl
> > >  create mode 100644 arch/x86/include/asm/acpi/pcr.asl
> > >  create mode 100644 arch/x86/include/asm/acpi/ramoops.asl
> >
> > There are recent (~June 2020) commits in coreboot which convert most ASL files
> > to ASL 2.0. The ASL 2.0 syntax is much easier to read IMHO, and I think it
> > would be good to update this patch to take advantage of the recent coreboot
> > developments. See e.g. the commit at [1].
> 
> Yes that looks nicer, but I have everything working and tested now so
> don't want to go back and unpick things. This seems like something we
> can pick up once we finally have this in the tree. The good thing is
> that this is just a syntax change as I understand it.

Fair enough. Yes, it should only be a syntax change.

Regardingn testing: I haven't tested individual patches of part D, but I have
tested the complete series. After applying the fix for the DSDT length my
ApolloLake board has booted reliably with ACPI enabled.

I have some remaining issues that I haven't gone after yet (e.g. I see a
machine check error in the log), but the board always boots.

> A WFH project has been putting a few Chromebooks in my lab, and I
> expect to put coral in there once everything lands. That should give
> us the confidence to make minor and major changes in future.
> 
> Regards,
> SImon
> 
> > [1] https://github.com/coreboot/coreboot/commit/03248033e7be6f81ad5b60ed21a60071aee32c67
> >

regards, Wolfgang