[PATCH] clk: rockchip: rk3399: implement getting wdt/alive clocks

[Kever Yang]

On 2020/9/17 下午5:42, Jack Mitchell wrote:
> In order to correctly calculate the designware watchdog
> timeouts, the watchdog clock is required. Implement required
> clocks to facilitate this.
>
> Signed-off-by: Jack Mitchell <ml at embed.me.uk>

Reviewed-by: Kever Yang <kever.yang at rock-chips.com>


Thanks,

- Kever

> ---
>   drivers/clk/rockchip/clk_rk3399.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index c8075e3dd2..4caa3bbdf5 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -241,6 +241,10 @@ enum {
>   	DCLK_VOP_DIV_CON_MASK           = 0xff,
>   	DCLK_VOP_DIV_CON_SHIFT          = 0,
>   
> +	/* CLKSEL_CON57 */
> +	PCLK_ALIVE_DIV_CON_SHIFT        = 0,
> +	PCLK_ALIVE_DIV_CON_MASK         = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
> +
>   	/* CLKSEL_CON58 */
>   	CLK_SPI_PLL_SEL_WIDTH = 1,
>   	CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
> @@ -875,6 +879,17 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
>   	return set_rate;
>   }
>   
> +static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
> +{
> +        u32 div, val;
> +
> +        val = readl(&cru->clksel_con[57]);
> +        div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
> +	       PCLK_ALIVE_DIV_CON_SHIFT;
> +
> +        return DIV_TO_RATE(GPLL_HZ, div);
> +}
> +
>   static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
>   {
>   	u32 div, val;
> @@ -944,6 +959,10 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
>   	case ACLK_GIC_PRE:
>   	case PCLK_DDR:
>   		break;
> +	case PCLK_ALIVE:
> +	case PCLK_WDT:
> +		rate = rk3399_alive_get_clk(priv->cru);
> +		break;
>   	default:
>   		log_debug("Unknown clock %lu\n", clk->id);
>   		return -ENOENT;
> @@ -1510,6 +1529,7 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
>   	case PLL_PPLL:
>   		return PPLL_HZ;
>   	case PCLK_RKPWM_PMU:
> +	case PCLK_WDT_M0_PMU:
>   		rate = rk3399_pwm_get_clk(priv->pmucru);
>   		break;
>   	case SCLK_I2C0_PMU: