[PATCH v1] arm: socfpga: fix Gen5 enable of EMAC via FPGA

[Ralph Siemsen]

An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines")

Signed-off-by: Ralph Siemsen <ralph.siemsen at linaro.org>

---
I reviewed the other #defines for gen5 and they seem correct.
I have NOT checked the defines for Arria 10 or Stratix 10!

 arch/arm/mach-socfpga/include/mach/system_manager_gen5.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
index 90cb465d13..a63a4ee27d 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
@@ -26,9 +26,9 @@ void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #define SYSMGR_GEN5_ECCGRP_OCRAM		0x144
 #define SYSMGR_GEN5_EMACIO			0x400
 #define SYSMGR_GEN5_NAND_USEFPGA		0x6f0
-#define SYSMGR_GEN5_RGMII0_USEFPGA		0x6f8
+#define SYSMGR_GEN5_RGMII1_USEFPGA		0x6f8
 #define SYSMGR_GEN5_SDMMC_USEFPGA		0x708
-#define SYSMGR_GEN5_RGMII1_USEFPGA		0x704
+#define SYSMGR_GEN5_RGMII0_USEFPGA		0x714
 #define SYSMGR_GEN5_SPIM1_USEFPGA		0x730
 #define SYSMGR_GEN5_SPIM0_USEFPGA		0x738
 
-- 
2.17.1