[PATCH 05/19] ARM: dts: imx8mm: Add power domain nodes

[Jaehoon Chung]

On 4/2/21 9:47 PM, Marek Vasut wrote:
> Add power domain nodes to DT.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Ye Li <ye.li at nxp.com>
> Cc: uboot-imx <uboot-imx at nxp.com>


Reviewed-by: Jaehoon Chung <jh80.chung at samsung.com>

Best Regards,
Jaehoon Chung

> ---
>  arch/arm/dts/imx8mm.dtsi                 | 73 ++++++++++++++++++++++++
>  include/dt-bindings/power/imx8mm-power.h | 22 +++++++
>  2 files changed, 95 insertions(+)
>  create mode 100644 include/dt-bindings/power/imx8mm-power.h
> 
> diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
> index fa2d73f1803..b142b80734d 100644
> --- a/arch/arm/dts/imx8mm.dtsi
> +++ b/arch/arm/dts/imx8mm.dtsi
> @@ -4,6 +4,8 @@
>   */
>  
>  #include <dt-bindings/clock/imx8mm-clock.h>
> +#include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/reset/imx8mq-reset.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -592,6 +594,75 @@
>  				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>  				#reset-cells = <1>;
>  			};
> +
> +			gpc: gpc at 303a0000 {
> +				compatible = "fsl,imx8mm-gpc";
> +				reg = <0x303a0000 0x10000>;
> +				interrupt-parent = <&gic>;
> +				interrupt-controller;
> +				#interrupt-cells = <3>;
> +
> +				pgc {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					pgc_hsiomix: power-domain at 0 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
> +						clocks = <&clk IMX8MM_CLK_USB_BUS>;
> +					};
> +
> +					pgc_pcie: power-domain at 1 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_otg1: power-domain at 2 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_otg2: power-domain at 3 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
> +						power-domains = <&pgc_hsiomix>;
> +					};
> +
> +					pgc_gpumix: power-domain at 4 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
> +						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> +						         <&clk IMX8MM_CLK_GPU_AHB>;
> +					};
> +
> +					pgc_gpu: power-domain at 5 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_GPU>;
> +						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
> +						         <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> +						         <&clk IMX8MM_CLK_GPU2D_ROOT>,
> +						         <&clk IMX8MM_CLK_GPU3D_ROOT>;
> +						resets = <&src IMX8MQ_RESET_GPU_RESET>;
> +						power-domains = <&pgc_gpumix>;
> +					};
> +
> +					dispmix_pd: power-domain at 10 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
> +						clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
> +							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
> +							 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
> +					};
> +
> +					mipi_pd: power-domain at 11 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
> +						power-domains = <&dispmix_pd>;
> +					};
> +				};
> +			};
>  		};
>  
>  		aips2: bus at 30400000 {
> @@ -940,6 +1011,7 @@
>  				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
>  				phys = <&usbphynop1>;
>  				fsl,usbmisc = <&usbmisc1 0>;
> +				power-domains = <&pgc_otg1>;
>  				status = "disabled";
>  			};
>  
> @@ -959,6 +1031,7 @@
>  				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
>  				phys = <&usbphynop2>;
>  				fsl,usbmisc = <&usbmisc2 0>;
> +				power-domains = <&pgc_otg2>;
>  				status = "disabled";
>  			};
>  
> diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
> new file mode 100644
> index 00000000000..fc9c2e16aad
> --- /dev/null
> +++ b/include/dt-bindings/power/imx8mm-power.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + *  Copyright (C) 2020 Pengutronix, Lucas Stach <kernel at pengutronix.de>
> + */
> +
> +#ifndef __DT_BINDINGS_IMX8MM_POWER_H__
> +#define __DT_BINDINGS_IMX8MM_POWER_H__
> +
> +#define IMX8MM_POWER_DOMAIN_HSIOMIX	0
> +#define IMX8MM_POWER_DOMAIN_PCIE	1
> +#define IMX8MM_POWER_DOMAIN_OTG1	2
> +#define IMX8MM_POWER_DOMAIN_OTG2	3
> +#define IMX8MM_POWER_DOMAIN_GPUMIX	4
> +#define IMX8MM_POWER_DOMAIN_GPU		5
> +#define IMX8MM_POWER_DOMAIN_VPUMIX	6
> +#define IMX8MM_POWER_DOMAIN_VPUG1	7
> +#define IMX8MM_POWER_DOMAIN_VPUG2	8
> +#define IMX8MM_POWER_DOMAIN_VPUH1	9
> +#define IMX8MM_POWER_DOMAIN_DISPMIX	10
> +#define IMX8MM_POWER_DOMAIN_MIPI	11
> +
> +#endif
>