[PATCH v1 11/15] mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT node

[Stefan Roese]

Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Aaron Williams <awilliams at marvell.com>
Cc: Chandrakala Chavva <cchavva at marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck at gmail.com>
---

 arch/mips/dts/mrvl,cn73xx.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 9f3dc615d66d..83e5cde044a7 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -246,5 +246,24 @@
 				  0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000	/* non-prefetchable memory */
 				  0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */
 		};
+
+		uctl at 118006c000000 {
+			compatible = "cavium,octeon-7130-sata-uctl", "simple-bus";
+			reg = <0x11800 0x6c000000 0x0 0x100>;
+			ranges; /* Direct mapping */
+			#address-cells = <2>;
+			#size-cells = <2>;
+			portmap = <0x3>;
+			staggered-spinup;
+			cavium,qlm-trim = "4,sata";
+
+			sata: sata at 16c0000000000 {
+				compatible = "cavium,octeon-7130-ahci";
+				reg = <0x16c00 0x00000000 0x0 0x200>;
+				#address-cells = <2>;
+				#size-cells = <2>;
+				interrupts = <0x6c010 4>;
+			};
+		};
 	};
 };
-- 
2.31.1