[PATCH v1 5/6] arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB
Stefan Roese
sr at denx.de
Thu Apr 8 11:27:49 CEST 2021
From: Konstantin Porotchkin <kostap at marvell.com>
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN9130 CRB. This is only the base port with not all
interfaces supported fully.
Signed-off-by: Konstantin Porotchkin <kostap at marvell.com>
Signed-off-by: Stefan Roese <sr at denx.de>
---
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/cn9130-crb-A.dts | 57 ++++++++
arch/arm/dts/cn9130-crb-B.dts | 61 ++++++++
arch/arm/dts/cn9130-crb.dtsi | 253 ++++++++++++++++++++++++++++++++++
arch/arm/dts/cn9130.dtsi | 73 ++++++++++
5 files changed, 447 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/cn9130-crb-A.dts
create mode 100644 arch/arm/dts/cn9130-crb-B.dts
create mode 100644 arch/arm/dts/cn9130-crb.dtsi
create mode 100644 arch/arm/dts/cn9130.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cedddd370f02..b8c6bd3a7ae6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -237,7 +237,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-gp.dtb \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
- armada-xp-theadorable.dtb
+ armada-xp-theadorable.dtb \
+ cn9130-crb-A.dtb \
+ cn9130-crb-B.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
new file mode 100644
index 000000000000..fa21ef314cba
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "CN9130-CRB-A";
+ compatible = "marvell,cn9130-crb-A",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy3 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy4 {
+ phy-type = <PHY_TYPE_SFI>;
+ phy-speed = <PHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_3_125G>;
+ };
+};
+
+&cp0_pcie0 {
+ num-lanes = <4>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts
new file mode 100644
index 000000000000..7cb587ada826
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb-B.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "CN9130-CRB-B";
+ compatible = "marvell,cn9130-crb-B",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_SATA0>;
+ };
+
+ phy3 {
+ phy-type = <PHY_TYPE_USB3_HOST1>;
+ };
+
+ phy4 {
+ phy-type = <PHY_TYPE_SFI>;
+ phy-speed = <PHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_3_125G>;
+ };
+};
+
+&cp0_sata0 {
+ status = "okay";
+};
+
+&cp0_pcie0 {
+ num-lanes = <1>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-crb.dtsi b/arch/arm/dts/cn9130-crb.dtsi
new file mode 100644
index 000000000000..657a934764ae
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130.dtsi" /* include SoC device tree */
+
+/ {
+ model = "CN9130-CRB";
+ compatible = "marvell,cn9130-crb",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp0_spi1;
+ gpio0 = &ap_gpio0;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
+ };
+
+ memory at 00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ cp0 {
+ config-space {
+ sdhci at 780000 {
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ };
+ cp0_reg_sd_vccq: cp0_sd_vccq at 0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_sd_vcc: cp0_sd_vcc at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/*
+ * AP related configuration
+ */
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10, 12]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 1 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC - U6 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-11] RGMII1
+ * [12-26] GPIO
+ * [27-30] SPI1
+ * [33] SD_PWR_OFF
+ * [34] CP_PCIE0_CLKREQn
+ * [35-38] I2C1 I2C0
+ * [39] GPIO
+ * [40-43] SMI/XSMI
+ * [44-46] GPIO
+ * [47] UART1_TX
+ * [48] GPIO
+ * [49] SD_HST_18_EN
+ * [50] GPIO
+ * [51] SD_PWR_0
+ * [52] PCIE_RSTn
+ * [53] UART1_RX
+ * [54,55] GPIO
+ * [56-61] SDIO
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 3 3 3 3 3 3 3 3 3 3
+ 3 3 0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 2 2 2
+ 2 0 0 6 9 2 2 2 2 0
+ 8 8 8 8 0 0 0 7 0 0xa
+ 0 0xa 9 7 0 0 0xe 0xe 0xe 0xe
+ 0xe 0xe 0>;
+
+ cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
+ marvell,pins = < 55 >;
+ marvell,function = <0>;
+ };
+
+ cp0_spi1_pins_crb: cp0-spi-pins-crb {
+ marvell,pins = < 27 28 29 30 >;
+ marvell,function = <2>;
+ };
+
+ cp0_smi_pins_crb: cp0-smi-pins-crb {
+ marvell,pins = < 40 41 >;
+ marvell,function = <8>;
+ };
+
+ cp0_xsmi_pins_crb: cp0-xsmi-pins-crb {
+ marvell,pins = < 42 43 >;
+ marvell,function = <8>;
+ };
+
+};
+
+/*
+ * CP0
+ */
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp0_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ status = "okay";
+};
+
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins_crb>;
+ bus-width = <4>;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ status = "okay";
+};
+
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins_crb>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>, /* CS0 */
+ <0 0xffffffff>, /* CS1 */
+ <0 0xffffffff>, /* CS2 */
+ <0 0xffffffff>; /* CS3 */
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor", "spi-flash";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition at 400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_utmi0 {
+ status = "okay";
+};
+
+&cp0_utmi1 {
+ status = "okay";
+};
+
+&cp0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_smi_pins_crb>;
+ status = "okay";
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+ switch6: ethernet-switch at 6 {
+ reg = <6>;
+ };
+};
+
+&cp0_xmdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_xsmi_pins_crb>;
+ status = "okay";
+ nbaset_phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ /* Disable it for now, as mainline does not support this IF yet */
+ status = "okay";
+ phy-mode = "sfi";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_ge1_rgmii_pins>;
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ /* Disable it for now, as mainline does not support this IF yet */
+ status = "okay";
+ phy = <&nbaset_phy0>;
+ phy-mode = "sgmii-2500";
+};
diff --git a/arch/arm/dts/cn9130.dtsi b/arch/arm/dts/cn9130.dtsi
new file mode 100644
index 000000000000..68b767a70639
--- /dev/null
+++ b/arch/arm/dts/cn9130.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+/*
+ * Device Tree file for the CN 9030 SoC, made of an AP806 Quad and
+ * one CP110.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-common.dtsi"
+#include "armada-ap807.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_BASE_OFFSET (0xf2000000)
+#define CP110_SPACE_SIZE (0x02000000)
+#define CP110_BASE (CP110_BASE_OFFSET + \
+ (CP110_NUM * CP110_SPACE_SIZE))
+
+#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ (0xe0000000 + (iface - 1) * 0x1000000))
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "Marvell CN 9030";
+ compatible = "marvell,armada70x0", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
+ marvell,function = <3>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_pca0_pins: cp0-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
--
2.31.1
More information about the U-Boot
mailing list