[PATCH v3 00/11] riscv: k210: Enable use of AI ram bank
Sean Anderson
seanga2 at gmail.com
Fri Apr 9 04:13:02 CEST 2021
This ram bank was previously unusable because PLL1 was not started correctly.
This series fixes that bug, and allows U-Boot to relocate into the AI ram. This
provides an extra 2M of space in which to load payloads. I've also added some
minor patches to bring the device tree and clock driver closer to what Linux has
(or will have).
The bypass clock turned out to be still necessary after all; I had neglected to
test with CLK_K210_SET_RATE enabled, and I didn't notice that the clock rate
wasn't actually getting set (oops). I've added a warning which will hopefully
make it more difficult to make such mistakes in the future.
Changes in v3:
- Add a warning if we can't assign rates
- Split off patchs for fdtdec_setup_mem_size_base_* into another series
- Eliminated separate RAM driver
- Rebased onto u-boot/next
Changes in v2:
- Don't re-enable the PLL
- Simplify PLL instantiation
- Modify clock tree so clint is a child of aclk
- Sync memory dts node with Linux
- Use correct aisram clock
Sean Anderson (11):
clk: Warn on failure to assign rate
clk: k210: Fix PLLs not being enabled
clk: k210: Fix PLL enable always getting taken
clk: k210: Remove k210_register_pll
clk: k210: Move the clint clock to under aclk
clk: Add support for the k210 clock driver pre-relocation
riscv: Enable some devices pre-relocation
riscv: Enable AI ram on K210
riscv: k210: Rename airam to aisram
riscv: k210: Use AI as the parent clock of aisram, not PLL1
riscv: Don't reserve AI ram in k210 dts
arch/riscv/dts/k210.dtsi | 22 +++++++---------------
board/sipeed/maix/maix.c | 14 ++++++++++++--
configs/sipeed_maix_bitm_defconfig | 2 ++
drivers/clk/clk-uclass.c | 11 +++++++----
drivers/clk/kendryte/clk.c | 26 ++++++++++++++------------
drivers/clk/kendryte/pll.c | 26 ++++----------------------
include/configs/sipeed-maix.h | 3 +--
include/kendryte/pll.h | 4 ----
8 files changed, 47 insertions(+), 61 deletions(-)
--
2.31.0
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