[v1 03/17] arm: socfpga: Add handoff data support for Intel N5X device

[Chee, Tien Fong]

Hi Ley Foon,

> -----Original Message-----
> From: Tan, Ley Foon <ley.foon.tan at intel.com>
> Sent: Monday, 5 April, 2021 3:17 PM
> To: Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com>; u-boot at lists.denx.de
> Cc: Marek Vasut <marex at denx.de>; See, Chin Liang
> <chin.liang.see at intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>; Westergreen, Dalon
> <dalon.westergreen at intel.com>; Simon Glass <sjg at chromium.org>; Gan,
> Yau Wai <yau.wai.gan at intel.com>
> Subject: RE: [v1 03/17] arm: socfpga: Add handoff data support for Intel N5X
> device
> 
> 
> 
> > -----Original Message-----
> > From: Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com>
> > Sent: Wednesday, March 31, 2021 10:39 PM
> > To: u-boot at lists.denx.de
> > Cc: Marek Vasut <marex at denx.de>; Tan, Ley Foon
> > <ley.foon.tan at intel.com>; See, Chin Liang <chin.liang.see at intel.com>;
> > Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> > <tien.fong.chee at intel.com>; Westergreen, Dalon
> > <dalon.westergreen at intel.com>; Simon Glass <sjg at chromium.org>; Gan,
> > Yau Wai <yau.wai.gan at intel.com>; Lim, Elly Siew Chin
> > <elly.siew.chin.lim at intel.com>
> > Subject: [v1 03/17] arm: socfpga: Add handoff data support for Intel
> > N5X device
> >
> > N5X support both HPS handoff data and DDR handoff data.
> > HPS handoff data support re-use Straix10 and Agilex code. DDR handoff
> > data is newly introduced for N5X.
> >
> > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim at intel.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 28
> > +++++++++++++++
> >  arch/arm/mach-socfpga/wrap_handoff_soc64.c         | 40
> > ++++++++++++++++++++++
> >  2 files changed, 68 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
> 
> 
> [...]
> 
> 
> > diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > index a7ad7a18ed..37b4c360fb 100644
> > --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
> > @@ -60,6 +60,46 @@ int socfpga_handoff_read(void *handoff_address,
> > void *table, u32 table_len,
> >  			debug("at addr  0x%p\n", (u32 *)handoff_address);
> >  			return -EPERM;
> >  		}
> > +	} else {
> > +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
> > +		temp = readl(handoff_address);
> > +		if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC) {
> > +			debug("%s: umctl2 handoff data =\n{\n",
> > +			      __func__);
> > +		} else if (temp == SOC64_HANDOFF_DDR_PHY_MAGIC) {
> > +			debug("%s: PHY handoff data =\n{\n",
> > +			      __func__);
> > +		} else if (temp ==
> > SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> > +			debug("%s: PHY engine handoff data =\n{\n",
> > +			      __func__);
> > +		}
> > +
> > +		debug("handoff table address = 0x%p table length = 0x%x\n",
> > +		      table_x32, table_len);
> > +
> > +		if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC ||
> > +		    temp == SOC64_HANDOFF_DDR_PHY_MAGIC ||
> > +		    temp ==
> > SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
> > +			for (i = 0; i < table_len; i++) {
> > +				*table_x32 = readl(handoff_address +
> > +
> > 	SOC64_HANDOFF_OFFSET_DATA +
> > +						(i * 4));
> > +
> > +				if (!(i % 2))
> > +					debug(" No.%d Addr 0x%08x: ", i,
> > +					      *table_x32);
> > +				else
> > +					debug(" 0x%08x\n", *table_x32);
> > +
> > +				table_x32++;
> > +			}
> > +			debug("\n}\n");
> > +		} else {
> > +			debug("%s: Cannot find HANDOFF MAGIC ",
> > __func__);
> > +			debug("at addr 0x%p\n", (u32 *)handoff_address);
> > +			return -EPERM;
> > +		}
> > +#endif
> >  	}
> >
> >  	return 0;
> 
> 1. Can we auto detect the endianness from the magic word?
> 2. Can merge or simplify  the big and little endian flow? Do swap when it is big
> endian.

Yes, we can do.

Regards,
Tien Fong
> 
> 
> Regards
> Ley Foon
> 
> 
> Regards
> Ley Foon