[PATCH v3 1/2] x86: fsp: Don't program MTRR for DRAM for FSP1

[Bin Meng]

On Mon, Aug 2, 2021 at 10:45 PM Simon Glass <sjg at chromium.org> wrote:
>
> On Mon, 2 Aug 2021 at 03:45, Bin Meng <bmeng.cn at gmail.com> wrote:
> >
> > There are several outstanding issues as to why this does not apply
> > to FSP1:
> >
> > * For FSP1, the system memory and reserved memory used by FSP are
> >   already programmed in the MTRR by FSP.
> > * The 'mtrr_top' mistakenly includes TSEG memory range that has the
> >   same RES_MEM_RESERVED resource type. Its address is programmed
> >   and reported by FSP to be near the top of 4 GiB space, which is
> >   not what we want for SDRAM.
> > * The call to mtrr_add_request() is not guaranteed to have its size
> >   to be exactly the power of 2. This causes reserved bits of the
> >   IA32_MTRR_PHYSMASK register to be written which generates #GP.
> >
> > For FSP2, it seems this is necessary as without this, U-Boot boot
> > process on Chromebook Coral goes very slowly.
> >
> > Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> >
> > ---
> >
> > (no changes since v2)
> >
> > Changes in v2:
> > - Keep programing MTRR to FSP2 only
> >
> >  arch/x86/lib/fsp/fsp_dram.c | 27 +++++++++++++++++++++++----
> >  1 file changed, 23 insertions(+), 4 deletions(-)
>
> Reviewed-by: Simon Glass <sjg at chromium.org>
> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
> Tested-by: Simon Glass <sjg at chromium.org>

applied to u-boot-x86, thanks!