[PATCH 1/4] arm64: dts: rockchip: px30: Sync Linux PX30.Core files

Jagan Teki jagan at amarulasolutions.com
Wed Aug 4 11:05:48 CEST 2021


Engicam PX30.Core SoM and it's associated Carrier board device tree
files are different than the one it present in U-Boot.

Let's Sync the same from Linux-5.14-rc3 with removal of unneeded
nodes to satisfy the build.

Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
---
 arch/arm/dts/Makefile                         |   4 +-
 ...dts => px30-engicam-px30-core-ctouch2.dts} |   4 +-
 ...ts => px30-engicam-px30-core-edimm2.2.dts} |   4 +-
 arch/arm/dts/px30-engicam-px30-core.dtsi      | 241 ++++++++++++++++++
 configs/px30-core-ctouch2-px30_defconfig      |   4 +-
 configs/px30-core-edimm2.2-px30_defconfig     |   4 +-
 6 files changed, 251 insertions(+), 10 deletions(-)
 rename arch/arm/dts/{px30-px30-core-ctouch2.dts => px30-engicam-px30-core-ctouch2.dts} (80%)
 rename arch/arm/dts/{px30-px30-core-edimm2.2.dts => px30-engicam-px30-core-edimm2.2.dts} (79%)
 create mode 100644 arch/arm/dts/px30-engicam-px30-core.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 537c96bf5b..1d35411aa8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -71,8 +71,8 @@ dtb-$(CONFIG_MACH_S700) += \
 dtb-$(CONFIG_ROCKCHIP_PX30) += \
 	px30-evb.dtb \
 	px30-firefly.dtb \
-	px30-px30-core-ctouch2.dtb \
-	px30-px30-core-edimm2.2.dtb \
+	px30-engicam-px30-core-ctouch2.dtb \
+	px30-engicam-px30-core-edimm2.2.dtb \
 	rk3326-odroid-go2.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3036) += \
diff --git a/arch/arm/dts/px30-px30-core-ctouch2.dts b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
similarity index 80%
rename from arch/arm/dts/px30-px30-core-ctouch2.dts
rename to arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
index 2da0128188..5a0ecb8fae 100644
--- a/arch/arm/dts/px30-px30-core-ctouch2.dts
+++ b/arch/arm/dts/px30-engicam-px30-core-ctouch2.dts
@@ -9,11 +9,11 @@
 /dts-v1/;
 #include "px30.dtsi"
 #include "px30-engicam-ctouch2.dtsi"
-#include "px30-px30-core.dtsi"
+#include "px30-engicam-px30-core.dtsi"
 
 / {
 	model = "Engicam PX30.Core C.TOUCH 2.0";
-	compatible = "engicam,px30-core-ctouch2", "engicam,px30-px30-core",
+	compatible = "engicam,px30-core-ctouch2", "engicam,px30-core",
 		     "rockchip,px30";
 
 	chosen {
diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
similarity index 79%
rename from arch/arm/dts/px30-px30-core-edimm2.2.dts
rename to arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
index c36280ce7f..e54d1e480d 100644
--- a/arch/arm/dts/px30-px30-core-edimm2.2.dts
+++ b/arch/arm/dts/px30-engicam-px30-core-edimm2.2.dts
@@ -8,11 +8,11 @@
 /dts-v1/;
 #include "px30.dtsi"
 #include "px30-engicam-edimm2.2.dtsi"
-#include "px30-px30-core.dtsi"
+#include "px30-engicam-px30-core.dtsi"
 
 / {
 	model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
-	compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
+	compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core",
 		     "rockchip,px30";
 
 	chosen {
diff --git a/arch/arm/dts/px30-engicam-px30-core.dtsi b/arch/arm/dts/px30-engicam-px30-core.dtsi
new file mode 100644
index 0000000000..7249871530
--- /dev/null
+++ b/arch/arm/dts/px30-engicam-px30-core.dtsi
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+	compatible = "engicam,px30-core", "rockchip,px30";
+
+	aliases {
+		mmc0 = &emmc;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	non-removable;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk809: pmic at 20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+
+		regulators {
+			vdd_log: DCDC_REG1 {
+				regulator-name = "vdd_log";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vdd_arm: DCDC_REG2 {
+				regulator-name = "vdd_arm";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <950000>;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_3v3: DCDC_REG4 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc3v3_sys: DCDC_REG5 {
+				regulator-name = "vcc3v3_sys";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc_1v0: LDO_REG1 {
+				regulator-name = "vcc_1v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc_1v8: LDO_REG2 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_1v0: LDO_REG3 {
+				regulator-name = "vdd_1v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1000000>;
+				};
+			};
+
+			vcc3v0_pmu: LDO_REG4 {
+				regulator-name = "vcc3v0_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcc3v3_lcd: SWITCH_REG1 {
+				regulator-boot-on;
+				regulator-name = "vcc3v3_lcd";
+			};
+
+			vcc5v0_host: SWITCH_REG2 {
+				regulator-name = "vcc5v0_host";
+				regulator-always-on;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+&io_domains {
+	vccio1-supply = <&vcc_3v3>;
+	vccio2-supply = <&vcc_3v3>;
+	vccio3-supply = <&vcc_3v3>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&pinctrl {
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc_3v3>;
+	pmuio2-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index aed790b6a6..16e4603859 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-ctouch2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-ctouch2"
 CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_PX30_CORE=y
@@ -21,7 +21,7 @@ CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-ctouch2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
 # CONFIG_CONSOLE_MUX is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 0340039ce7..1ac39055f6 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
+CONFIG_DEFAULT_DEVICE_TREE="px30-engicam-px30-core-edimm2.2"
 CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_PX30_CORE=y
@@ -21,7 +21,7 @@ CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
 # CONFIG_CONSOLE_MUX is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-- 
2.25.1



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