[PATCH v2 2/6] board: sifive: use ccache driver instead of helper function

Zong Li zong.li at sifive.com
Tue Aug 10 08:40:27 CEST 2021


On Tue, Aug 10, 2021 at 12:51 PM Sean Anderson <seanga2 at gmail.com> wrote:
>
> On 8/3/21 12:44 AM, Zong Li wrote:
> > Invokes the generic cache_enable interface to execute the relative
> > implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li <zong.li at sifive.com>
> > ---
> >   arch/riscv/cpu/fu540/Kconfig              |  1 +
> >   arch/riscv/cpu/fu540/cache.c              | 54 ++++++-----------------
> >   arch/riscv/cpu/fu740/Kconfig              |  1 +
> >   arch/riscv/cpu/fu740/cache.c              | 52 ++++++----------------
> >   arch/riscv/include/asm/arch-fu540/cache.h |  2 +-
> >   arch/riscv/include/asm/arch-fu740/cache.h |  2 +-
> >   board/sifive/unleashed/unleashed.c        | 10 +----
> >   board/sifive/unmatched/unmatched.c        |  9 +---
> >   8 files changed, 33 insertions(+), 98 deletions(-)
> >
> > diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
> > index 05463b2625..8608741779 100644
> > --- a/arch/riscv/cpu/fu540/Kconfig
> > +++ b/arch/riscv/cpu/fu540/Kconfig
> > @@ -19,6 +19,7 @@ config SIFIVE_FU540
> >       imply SMP
> >       imply CLK_SIFIVE
> >       imply CLK_SIFIVE_PRCI
> > +     imply SIFIVE_CCACHE
> >       imply SIFIVE_SERIAL
> >       imply MACB
> >       imply MII
> > diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
> > index 0fc4ef6c00..bc31f664b8 100644
> > --- a/arch/riscv/cpu/fu540/cache.c
> > +++ b/arch/riscv/cpu/fu540/cache.c
> > @@ -1,55 +1,29 @@
> >   // SPDX-License-Identifier: GPL-2.0+
> >   /*
> > - * Copyright (C) 2020 SiFive, Inc
> > + * Copyright (C) 2020 - 2021 SiFive, Inc
> >    *
> >    * Authors:
> >    *   Pragnesh Patel <pragnesh.patel at sifive.com>
> >    */
> >
> >   #include <common.h>
> > -#include <asm/global_data.h>
> > -#include <asm/io.h>
> > -#include <linux/bitops.h>
> > +#include <cache.h>
> > +#include <dm.h>
> >
> > -/* Register offsets */
> > -#define L2_CACHE_CONFIG      0x000
> > -#define L2_CACHE_ENABLE      0x008
> > -
> > -#define MASK_NUM_WAYS        GENMASK(15, 8)
> > -#define NUM_WAYS_SHIFT       8
> > -
> > -DECLARE_GLOBAL_DATA_PTR;
> > -
> > -int cache_enable_ways(void)
> > +int sifive_ccache_enable_ways(void)
> >   {
> > -     const void *blob = gd->fdt_blob;
> > -     int node;
> > -     fdt_addr_t base;
> > -     u32 config;
> > -     u32 ways;
> > -
> > -     volatile u32 *enable;
> > -
> > -     node = fdt_node_offset_by_compatible(blob, -1,
> > -                                          "sifive,fu540-c000-ccache");
> > -
> > -     if (node < 0)
> > -             return node;
> > -
> > -     base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
> > -                                             NULL, false);
> > -     if (base == FDT_ADDR_T_NONE)
> > -             return FDT_ADDR_T_NONE;
> > +     struct udevice *dev;
> > +     int ret;
> >
> > -     config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
> > -     ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
> > +     ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +                                       DM_DRIVER_GET(sifive_ccache),
> > +                                       &dev);
> > +     if (ret)
> > +             return log_msg_ret("Cannot enable cache ways", ret);
> >
> > -     enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
> > +     ret = cache_enable(dev);
> > +     if (ret)
> > +             return log_msg_ret("ccache enable failed", ret);
> >
> > -     /* memory barrier */
> > -     mb();
> > -     (*enable) = ways - 1;
> > -     /* memory barrier */
> > -     mb();
> >       return 0;
> >   }
> > diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
> > index 408195f149..b4cada0ea9 100644
> > --- a/arch/riscv/cpu/fu740/Kconfig
> > +++ b/arch/riscv/cpu/fu740/Kconfig
> > @@ -19,6 +19,7 @@ config SIFIVE_FU740
> >       imply SMP
> >       imply CLK_SIFIVE
> >       imply CLK_SIFIVE_PRCI
> > +     imply SIFIVE_CCACHE
> >       imply SIFIVE_SERIAL
> >       imply MACB
> >       imply MII
> > diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
> > index 680955c9e3..e2782d76c0 100644
> > --- a/arch/riscv/cpu/fu740/cache.c
> > +++ b/arch/riscv/cpu/fu740/cache.c
> > @@ -7,49 +7,23 @@
> >    */
> >
> >   #include <common.h>
> > -#include <asm/io.h>
> > -#include <linux/bitops.h>
> > -#include <asm/global_data.h>
> > +#include <cache.h>
> > +#include <dm.h>
> >
> > -/* Register offsets */
> > -#define L2_CACHE_CONFIG      0x000
> > -#define L2_CACHE_ENABLE      0x008
> > -
> > -#define MASK_NUM_WAYS        GENMASK(15, 8)
> > -#define NUM_WAYS_SHIFT       8
> > -
> > -DECLARE_GLOBAL_DATA_PTR;
> > -
> > -int cache_enable_ways(void)
> > +int sifive_ccache_enable_ways(void)
> >   {
> > -     const void *blob = gd->fdt_blob;
> > -     int node;
> > -     fdt_addr_t base;
> > -     u32 config;
> > -     u32 ways;
> > -
> > -     volatile u32 *enable;
> > -
> > -     node = fdt_node_offset_by_compatible(blob, -1,
> > -                                          "sifive,fu740-c000-ccache");
> > -
> > -     if (node < 0)
> > -             return node;
> > -
> > -     base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
> > -                                             NULL, false);
> > -     if (base == FDT_ADDR_T_NONE)
> > -             return FDT_ADDR_T_NONE;
> > +     struct udevice *dev;
> > +     int ret;
> >
> > -     config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
> > -     ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
> > +     ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +                                       DM_DRIVER_GET(sifive_ccache),
> > +                                       &dev);
> > +     if (ret)
> > +             return log_msg_ret("Cannot enable cache ways", ret);
> >
> > -     enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
> > +     ret = cache_enable(dev);
> > +     if (ret)
> > +             return log_msg_ret("ccache enable failed", ret);
> >
> > -     /* memory barrier */
> > -     mb();
> > -     (*enable) = ways - 1;
> > -     /* memory barrier */
> > -     mb();
> >       return 0;
> >   }
> > diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h
> > index 135a17c679..c252eb64d1 100644
> > --- a/arch/riscv/include/asm/arch-fu540/cache.h
> > +++ b/arch/riscv/include/asm/arch-fu540/cache.h
> > @@ -9,6 +9,6 @@
> >   #ifndef _CACHE_SIFIVE_H
> >   #define _CACHE_SIFIVE_H
> >
> > -int cache_enable_ways(void);
> > +int sifive_ccache_enable_ways(void);
> >
> >   #endif /* _CACHE_SIFIVE_H */
> > diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h
> > index 7d4fe9942b..8c456e3658 100644
> > --- a/arch/riscv/include/asm/arch-fu740/cache.h
> > +++ b/arch/riscv/include/asm/arch-fu740/cache.h
> > @@ -9,6 +9,6 @@
> >   #ifndef _CACHE_SIFIVE_H
> >   #define _CACHE_SIFIVE_H
> >
> > -int cache_enable_ways(void);
> > +int sifive_ccache_enable_ways(void);
> >
> >   #endif /* _CACHE_SIFIVE_H */
> > diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c
> > index 43027f0b54..12e61ec85f 100644
> > --- a/board/sifive/unleashed/unleashed.c
> > +++ b/board/sifive/unleashed/unleashed.c
> > @@ -126,14 +126,6 @@ void *board_fdt_blob_setup(void)
> >
> >   int board_init(void)
> >   {
> > -     int ret;
> > -
> >       /* enable all cache ways */
> > -     ret = cache_enable_ways();
> > -     if (ret) {
> > -             debug("%s: could not enable cache ways\n", __func__);
> > -             return ret;
> > -     }
> > -
> > -     return 0;
> > +     return sifive_ccache_enable_ways();
> >   }
> > diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
> > index 2f5629b578..d27c4d3e88 100644
> > --- a/board/sifive/unmatched/unmatched.c
> > +++ b/board/sifive/unmatched/unmatched.c
> > @@ -23,13 +23,6 @@ void *board_fdt_blob_setup(void)
> >
> >   int board_init(void)
> >   {
> > -     int ret;
> > -
> >       /* enable all cache ways */
> > -     ret = cache_enable_ways();
> > -     if (ret) {
> > -             debug("%s: could not enable cache ways\n", __func__);
> > -             return ret;
> > -     }
> > -     return 0;
> > +     return sifive_ccache_enable_ways();
> >   }
> >
>
> Can you combine patches 2-4 in some way? It seems like you add some code only to immediately refactor it.
>

Okay, let me tidy up these patches. I separated them because I'd like
to separate the histories of using ccache driver and using common
interfaces, so people could easily know the process of evolution. But
yes, I might as well re-split the patches and combine them.


> --Sean


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