[PATCH] usb: dwc2: Rename CONFIG_DWC2 namespace to DWC2
Tom Rini
trini at konsulko.com
Tue Aug 10 22:17:55 CEST 2021
There are a number of DWC2 configuration options that are set in dwc2.h
and referenced in dwc2.c only. Move these out of the CONFIG_DWC2
namespace and in to the DWC2 namespace. Note that hikey was defining an
option that was already always enabled, so we can remove that hunk.
Cc: Marek Vasut <marex at denx.de>
Signed-off-by: Tom Rini <trini at konsulko.com>
---
drivers/usb/host/dwc2.c | 52 ++++++++++++++++++------------------
drivers/usb/host/dwc2.h | 42 ++++++++++++++---------------
include/configs/hikey.h | 4 ---
scripts/config_whitelist.txt | 20 --------------
4 files changed, 47 insertions(+), 71 deletions(-)
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 43cc2e04339c..23060fc369c0 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -86,14 +86,14 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
{
uint32_t phyclk;
-#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
#else
/* High speed PHY running at full speed or high speed */
phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
#endif
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(®s->ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
@@ -257,28 +257,28 @@ static void dwc_otg_core_host_init(struct udevice *dev,
/* Initialize Host Configuration Register */
init_fslspclksel(regs);
-#ifdef CONFIG_DWC2_DFLT_SPEED_FULL
+#ifdef DWC2_DFLT_SPEED_FULL
setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
#endif
/* Configure data FIFO sizes */
-#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#ifdef DWC2_ENABLE_DYNAMIC_FIFO
if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
/* Rx FIFO */
- writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
+ writel(DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
/* Non-periodic Tx FIFO */
- nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
+ nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
DWC2_FIFOSIZE_DEPTH_OFFSET;
- nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
+ nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(nptxfifosize, ®s->gnptxfsiz);
/* Periodic Tx FIFO */
- ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
+ ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE <<
DWC2_FIFOSIZE_DEPTH_OFFSET;
- ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
- CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
+ ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE +
+ DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
DWC2_FIFOSIZE_STARTADDR_OFFSET;
writel(ptxfifosize, ®s->hptxfsiz);
}
@@ -340,7 +340,7 @@ static void dwc_otg_core_init(struct udevice *dev)
struct dwc2_core_regs *regs = priv->regs;
uint32_t ahbcfg = 0;
uint32_t usbcfg = 0;
- uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
+ uint8_t brst_sz = DWC2_DMA_BURST_SIZE;
/* Common Initialization */
usbcfg = readl(®s->gusbcfg);
@@ -357,7 +357,7 @@ static void dwc_otg_core_init(struct udevice *dev)
}
/* Set external TS Dline pulsing */
-#ifdef CONFIG_DWC2_TS_DLINE
+#ifdef DWC2_TS_DLINE
usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
#else
usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
@@ -371,8 +371,8 @@ static void dwc_otg_core_init(struct udevice *dev)
* This programming sequence needs to happen in FS mode before
* any other programming occurs
*/
-#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
- (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
+#if defined(DWC2_DFLT_SPEED_FULL) && \
+ (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
/* If FS mode with FS PHY */
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
@@ -387,7 +387,7 @@ static void dwc_otg_core_init(struct udevice *dev)
if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
init_fslspclksel(regs);
-#ifdef CONFIG_DWC2_I2C_ENABLE
+#ifdef DWC2_I2C_ENABLE
/* Program GUSBCFG.OtgUtmifsSel to I2C */
setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
@@ -407,16 +407,16 @@ static void dwc_otg_core_init(struct udevice *dev)
* immediately after setting phyif.
*/
usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
- usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
+ usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
-#ifdef CONFIG_DWC2_PHY_ULPI_DDR
+#ifdef DWC2_PHY_ULPI_DDR
usbcfg |= DWC2_GUSBCFG_DDRSEL;
#else
usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
#endif
} else { /* UTMI+ interface */
-#if (CONFIG_DWC2_UTMI_WIDTH == 16)
+#if (DWC2_UTMI_WIDTH == 16)
usbcfg |= DWC2_GUSBCFG_PHYIF;
#endif
}
@@ -429,7 +429,7 @@ static void dwc_otg_core_init(struct udevice *dev)
usbcfg = readl(®s->gusbcfg);
usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
-#ifdef CONFIG_DWC2_ULPI_FS_LS
+#ifdef DWC2_ULPI_FS_LS
uint32_t hwcfg2 = readl(®s->ghwcfg2);
uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
@@ -456,14 +456,14 @@ static void dwc_otg_core_init(struct udevice *dev)
brst_sz >>= 1;
}
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
#endif
break;
case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
-#ifdef CONFIG_DWC2_DMA_ENABLE
+#ifdef DWC2_DMA_ENABLE
ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
#endif
break;
@@ -476,7 +476,7 @@ static void dwc_otg_core_init(struct udevice *dev)
if (!priv->hnp_srp_disable)
usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
-#ifdef CONFIG_DWC2_IC_USB_CAP
+#ifdef DWC2_IC_USB_CAP
usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
#endif
@@ -939,9 +939,9 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
in, len);
- max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
- if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
- max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+ max_xfer_len = DWC2_MAX_PACKET_COUNT * max;
+ if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE)
+ max_xfer_len = DWC2_MAX_TRANSFER_SIZE;
if (max_xfer_len > DWC2_DATA_BUF_SIZE)
max_xfer_len = DWC2_DATA_BUF_SIZE;
@@ -1198,7 +1198,7 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
return -ENODEV;
}
-#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
+#ifdef DWC2_PHY_ULPI_EXT_VBUS
priv->ext_vbus = 1;
#else
priv->ext_vbus = 0;
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index 97a06c48f216..a6f562fe60e2 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -759,32 +759,32 @@ struct dwc2_core_regs {
#define RH_B_PPCM 0xffff0000 /* port power control mask */
/* Default driver configuration */
-#define CONFIG_DWC2_DMA_ENABLE
-#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
-#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
-#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
-#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */
-#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS)
-#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
-#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
-#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535
-#define CONFIG_DWC2_MAX_PACKET_COUNT 511
+#define DWC2_DMA_ENABLE
+#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */
+#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */
+#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */
+#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */
+#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS)
+#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */
+#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */
+#define DWC2_MAX_TRANSFER_SIZE 65535
+#define DWC2_MAX_PACKET_COUNT 511
#define DWC2_PHY_TYPE_FS 0
#define DWC2_PHY_TYPE_UTMI 1
#define DWC2_PHY_TYPE_ULPI 2
-#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
-#ifndef CONFIG_DWC2_UTMI_WIDTH
-#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
+#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */
+#ifndef DWC2_UTMI_WIDTH
+#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */
#endif
-#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
-#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
-#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */
-#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */
-#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */
-#undef CONFIG_DWC2_THR_CTL /* Threshold control */
-#define CONFIG_DWC2_TX_THR_LENGTH 64
-#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */
+#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */
+#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */
+#undef DWC2_I2C_ENABLE /* Enable I2C */
+#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */
+#undef DWC2_TS_DLINE /* External DLine pulsing */
+#undef DWC2_THR_CTL /* Threshold control */
+#define DWC2_TX_THR_LENGTH 64
+#undef DWC2_IC_USB_CAP /* IC Cap */
#endif /* __DWC2_H__ */
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 659fbee052d5..45b01463acb1 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -47,10 +47,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-#ifdef CONFIG_USB_DWC2
-#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
-#endif
-
#define CONFIG_HIKEY_GPIO
/* BOOTP options */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 2d70bf5da7c5..9384aa8e4e0b 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -282,26 +282,6 @@ CONFIG_DRIVER_AT91EMAC_PHYADDR
CONFIG_DRIVER_AT91EMAC_QUIET
CONFIG_DRIVER_DM9000
CONFIG_DSP_CLUSTER_START
-CONFIG_DWC2_DFLT_SPEED_FULL
-CONFIG_DWC2_DMA_BURST_SIZE
-CONFIG_DWC2_DMA_ENABLE
-CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
-CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
-CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE
-CONFIG_DWC2_HOST_RX_FIFO_SIZE
-CONFIG_DWC2_I2C_ENABLE
-CONFIG_DWC2_IC_USB_CAP
-CONFIG_DWC2_MAX_CHANNELS
-CONFIG_DWC2_MAX_PACKET_COUNT
-CONFIG_DWC2_MAX_TRANSFER_SIZE
-CONFIG_DWC2_PHY_TYPE
-CONFIG_DWC2_PHY_ULPI_DDR
-CONFIG_DWC2_PHY_ULPI_EXT_VBUS
-CONFIG_DWC2_THR_CTL
-CONFIG_DWC2_TS_DLINE
-CONFIG_DWC2_TX_THR_LENGTH
-CONFIG_DWC2_ULPI_FS_LS
-CONFIG_DWC2_UTMI_WIDTH
CONFIG_DWCDDR21MCTL
CONFIG_DWCDDR21MCTL_BASE
CONFIG_DWC_AHSATA_BASE_ADDR
--
2.17.1
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